Commit 6cd4b7cf authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Nishanth Menon
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arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G 



Add device tree support to enable MCU CPSW with J784S4 EVM.

Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: default avatarAndrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230315042548.1500528-1-s-vadapalli@ti.com


Signed-off-by: default avatarNishanth Menon <nm@ti.com>
parent cf2aacfe

arch/arm64/boot/dts/ti/k3-j784s4-evm.dts

+50 −0
Original line number Diff line number Diff line
@@ -140,6 +140,32 @@ 
	};

};



&wkup_pmx0 {

	mcu_cpsw_pins_default: mcu-cpsw-pins-default {

		pinctrl-single,pins = <

			J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */

			J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */

			J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */

			J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */

			J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */

			J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */

			J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */

			J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */

			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */

			J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */

			J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */

			J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */

		>;

	};



	mcu_mdio_pins_default: mcu-mdio-pins-default {

		pinctrl-single,pins = <

			J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */

			J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */

		>;

	};

};



&main_uart8 {

	status = "okay";

	pinctrl-names = "default";
@@ -194,3 +220,27 @@ 
&main_gpio0 {

	status = "okay";

};



&mcu_cpsw {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&mcu_cpsw_pins_default>;

};



&davinci_mdio {

	pinctrl-names = "default";

	pinctrl-0 = <&mcu_mdio_pins_default>;



	mcu_phy0: ethernet-phy@0 {

		reg = <0>;

		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

		ti,min-output-impedance;

	};

};



&mcu_cpsw_port1 {

	status = "okay";

	phy-mode = "rgmii-rxid";

	phy-handle = <&mcu_phy0>;

};