Commit 6ca2b9ca authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/sysreg: Add _EL1 into ID_AA64PFR1_EL1 constant names 



Our standard is to include the _EL1 in the constant names for registers but
we did not do that for ID_AA64PFR1_EL1, update to do so in preparation for
conversion to automatic generation. No functional change.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-8-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 55adc08d

arch/arm64/include/asm/cpufeature.h

+3 −3
Original line number Diff line number Diff line
@@ -624,16 +624,16 @@ static inline bool id_aa64pfr0_sve(u64 pfr0) 


static inline bool id_aa64pfr1_sme(u64 pfr1)

{

	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_SME_SHIFT);

	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_SME_SHIFT);



	return val > 0;

}



static inline bool id_aa64pfr1_mte(u64 pfr1)

{

	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_MTE_SHIFT);

	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT);



	return val >= ID_AA64PFR1_MTE;

	return val >= ID_AA64PFR1_EL1_MTE;

}



void __init setup_cpu_features(void);

arch/arm64/include/asm/el2_setup.h

+1 −1
Original line number Diff line number Diff line
@@ -149,7 +149,7 @@ 


	mov	x0, xzr

	mrs	x1, id_aa64pfr1_el1

	ubfx	x1, x1, #ID_AA64PFR1_SME_SHIFT, #4

	ubfx	x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4

	cbz	x1, .Lset_fgt_\@



	/* Disable nVHE traps of TPIDR2 and SMPRI */

arch/arm64/include/asm/sysreg.h

+17 −17
Original line number Diff line number Diff line
@@ -714,23 +714,23 @@ 
#define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2



/* id_aa64pfr1 */

#define ID_AA64PFR1_SME_SHIFT		24

#define ID_AA64PFR1_MPAMFRAC_SHIFT	16

#define ID_AA64PFR1_RASFRAC_SHIFT	12

#define ID_AA64PFR1_MTE_SHIFT		8

#define ID_AA64PFR1_SSBS_SHIFT		4

#define ID_AA64PFR1_BT_SHIFT		0



#define ID_AA64PFR1_SSBS_PSTATE_NI	0

#define ID_AA64PFR1_SSBS_PSTATE_ONLY	1

#define ID_AA64PFR1_SSBS_PSTATE_INSNS	2

#define ID_AA64PFR1_BT_BTI		0x1

#define ID_AA64PFR1_SME			1



#define ID_AA64PFR1_MTE_NI		0x0

#define ID_AA64PFR1_MTE_EL0		0x1

#define ID_AA64PFR1_MTE			0x2

#define ID_AA64PFR1_MTE_ASYMM		0x3

#define ID_AA64PFR1_EL1_SME_SHIFT	24

#define ID_AA64PFR1_EL1_MPAMFRAC_SHIFT	16

#define ID_AA64PFR1_EL1_RASFRAC_SHIFT	12

#define ID_AA64PFR1_EL1_MTE_SHIFT	8

#define ID_AA64PFR1_EL1_SSBS_SHIFT	4

#define ID_AA64PFR1_EL1_BT_SHIFT	0



#define ID_AA64PFR1_EL1_SSBS_PSTATE_NI		0

#define ID_AA64PFR1_EL1_SSBS_PSTATE_ONLY	1

#define ID_AA64PFR1_EL1_SSBS_PSTATE_INSNS	2

#define ID_AA64PFR1_EL1_BT_BTI			0x1

#define ID_AA64PFR1_EL1_SME			1



#define ID_AA64PFR1_EL1_MTE_NI		0x0

#define ID_AA64PFR1_EL1_MTE_EL0		0x1

#define ID_AA64PFR1_EL1_MTE		0x2

#define ID_AA64PFR1_EL1_MTE_ASYMM	0x3



/* id_aa64mmfr0 */

#define ID_AA64MMFR0_EL1_ECV_SHIFT		60

arch/arm64/kernel/cpufeature.c

+21 −21
Original line number Diff line number Diff line
@@ -264,14 +264,14 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 


static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SME_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAMFRAC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RASFRAC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_PSTATE_NI),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),

				    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),

				    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0),

	ARM64_FTR_END,

};
@@ -2367,10 +2367,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64PFR1_EL1,

		.field_pos = ID_AA64PFR1_SSBS_SHIFT,

		.field_pos = ID_AA64PFR1_EL1_SSBS_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,

		.min_field_value = ID_AA64PFR1_EL1_SSBS_PSTATE_ONLY,

	},

#ifdef CONFIG_ARM64_CNP

	{
@@ -2528,9 +2528,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = has_cpuid_feature,

		.cpu_enable = bti_enable,

		.sys_reg = SYS_ID_AA64PFR1_EL1,

		.field_pos = ID_AA64PFR1_BT_SHIFT,

		.field_pos = ID_AA64PFR1_EL1_BT_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64PFR1_BT_BTI,

		.min_field_value = ID_AA64PFR1_EL1_BT_BTI,

		.sign = FTR_UNSIGNED,

	},

#endif
@@ -2541,9 +2541,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,

		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64PFR1_EL1,

		.field_pos = ID_AA64PFR1_MTE_SHIFT,

		.field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64PFR1_MTE,

		.min_field_value = ID_AA64PFR1_EL1_MTE,

		.sign = FTR_UNSIGNED,

		.cpu_enable = cpu_enable_mte,

	},
@@ -2553,9 +2553,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,

		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64PFR1_EL1,

		.field_pos = ID_AA64PFR1_MTE_SHIFT,

		.field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64PFR1_MTE_ASYMM,

		.min_field_value = ID_AA64PFR1_EL1_MTE_ASYMM,

		.sign = FTR_UNSIGNED,

	},

#endif /* CONFIG_ARM64_MTE */
@@ -2577,9 +2577,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.capability = ARM64_SME,

		.sys_reg = SYS_ID_AA64PFR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64PFR1_SME_SHIFT,

		.field_pos = ID_AA64PFR1_EL1_SME_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64PFR1_SME,

		.min_field_value = ID_AA64PFR1_EL1_SME,

		.matches = has_cpuid_feature,

		.cpu_enable = sme_kernel_enable,

	},
@@ -2739,24 +2739,24 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),

	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),

#endif

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),

#ifdef CONFIG_ARM64_BTI

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),

#endif

#ifdef CONFIG_ARM64_PTR_AUTH

	HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),

	HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),

#endif

#ifdef CONFIG_ARM64_MTE

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),

#endif /* CONFIG_ARM64_MTE */

	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),

	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),

	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),

	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),

#ifdef CONFIG_ARM64_SME

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),

	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),

	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),

	HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),

arch/arm64/kernel/hyp-stub.S

+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ SYM_CODE_START_LOCAL(__finalise_el2) 
	msr_s	SYS_ZCR_EL2, x1			// length for EL1.



.Lskip_sve:

	check_override id_aa64pfr1 ID_AA64PFR1_SME_SHIFT .Linit_sme .Lskip_sme

	check_override id_aa64pfr1 ID_AA64PFR1_EL1_SME_SHIFT .Linit_sme .Lskip_sme



.Linit_sme:	/* SME register access and priority mapping */

	mrs	x0, cptr_el2			// Disable SME traps