Commit 6c873654 authored by Yassine Oudjana's avatar Yassine Oudjana Committed by Linus Walleij
Browse files

dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add MT6797 



Combine MT6797 pin controller document into MT6779 one. reg and
reg-names property constraints are set using conditionals.
A conditional is also used to make interrupt-related properties
required on the MT6779 pin controller only, since the MT6797
controller doesn't support interrupts (or not yet, at least).
drive-strength and slew-rate properties which weren't described
in the MT6779 document before are brought in from the MT6797 one.
Both pin controllers share a common driver core so they should
both support these properties.

Signed-off-by: default avatarYassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221028153505.23741-5-y.oudjana@protonmail.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 7e63d92d

Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml

+66 −21
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: Mediatek MT6779 Pin Controller 


maintainers:

  - Andy Teng <andy.teng@mediatek.com>

  - Sean Wang <sean.wang@kernel.org>



description:

  The MediaTek pin controller on MT6779 is used to control pin
@@ -15,23 +16,14 @@ description: 


properties:

  compatible:

    const: mediatek,mt6779-pinctrl

    enum:

      - mediatek,mt6779-pinctrl

      - mediatek,mt6797-pinctrl



  reg:

    minItems: 9

    maxItems: 9

    description: Physical addresses for GPIO base(s) and EINT registers.



  reg-names:

    items:

      - const: "gpio"

      - const: "iocfg_rm"

      - const: "iocfg_br"

      - const: "iocfg_lm"

      - const: "iocfg_lb"

      - const: "iocfg_rt"

      - const: "iocfg_lt"

      - const: "iocfg_tl"

      - const: "eint"

  reg-names: true



  gpio-controller: true
@@ -58,17 +50,64 @@ properties: 
  "#interrupt-cells":

    const: 2



allOf:

  - $ref: "pinctrl.yaml#"



required:

  - compatible

  - reg

  - reg-names

  - gpio-controller

  - "#gpio-cells"

  - interrupt-controller



allOf:

  - $ref: "pinctrl.yaml#"

  - if:

      properties:

        compatible:

          contains:

            const: mediatek,mt6779-pinctrl

    then:

      properties:

        reg:

          minItems: 9

          maxItems: 9



        reg-names:

          items:

            - const: gpio

            - const: iocfg_rm

            - const: iocfg_br

            - const: iocfg_lm

            - const: iocfg_lb

            - const: iocfg_rt

            - const: iocfg_lt

            - const: iocfg_tl

            - const: eint

  - if:

      properties:

        compatible:

          contains:

            const: mediatek,mt6797-pinctrl

    then:

      properties:

        reg:

          minItems: 5

          maxItems: 5



        reg-names:

          items:

            - const: gpio

            - const: iocfgl

            - const: iocfgb

            - const: iocfgr

            - const: iocfgt

  - if:

      properties:

        reg-names:

          contains:

            const: eint

    then:

      required:

        - interrupts

        - interrupt-controller

        - "#interrupt-cells"



patternProperties:
@@ -111,6 +150,12 @@ patternProperties: 


          input-schmitt-disable: true



          drive-strength:

            enum: [2, 4, 8, 12, 16]



          slew-rate:

            enum: [0, 1]



          mediatek,pull-up-adv:

            description: |

              Pull up setings for 2 pull resistors, R0 and R1. User can

Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml

deleted100644 → 0
+0 −176
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mediatek MT6797 Pin Controller



maintainers:

  - Sean Wang <sean.wang@kernel.org>



description: |+

  The MediaTek's MT6797 Pin controller is used to control SoC pins.



properties:

  compatible:

    const: mediatek,mt6797-pinctrl



  reg:

    minItems: 5

    maxItems: 5



  reg-names:

    items:

      - const: gpio

      - const: iocfgl

      - const: iocfgb

      - const: iocfgr

      - const: iocfgt



  gpio-controller: true



  "#gpio-cells":

    const: 2

    description: |

      Number of cells in GPIO specifier. Since the generic GPIO

      binding is used, the amount of cells must be specified as 2. See the below

      mentioned gpio binding representation for description of particular cells.



  interrupt-controller: true



  interrupts:

    maxItems: 1



  "#interrupt-cells":

    const: 2



allOf:

  - $ref: "pinctrl.yaml#"



required:

  - compatible

  - reg

  - reg-names

  - gpio-controller

  - "#gpio-cells"



patternProperties:

  '-[0-9]+$':

    type: object

    additionalProperties: false

    patternProperties:

      'pins':

        type: object

        additionalProperties: false

        description: |

          A pinctrl node should contain at least one subnodes representing the

          pinctrl groups available on the machine. Each subnode will list the

          pins it needs, and how they should be configured, with regard to muxer

          configuration, pullups, drive strength, input enable/disable and input

          schmitt.

        $ref: "/schemas/pinctrl/pincfg-node.yaml"



        properties:

          pinmux:

            description:

              integer array, represents gpio pin number and mux setting.

              Supported pin number and mux varies for different SoCs, and are

              defined as macros in <soc>-pinfunc.h directly.



          bias-disable: true



          bias-pull-up: true



          bias-pull-down: true



          input-enable: true



          input-disable: true



          output-enable: true



          output-low: true



          output-high: true



          input-schmitt-enable: true



          input-schmitt-disable: true



          drive-strength:

            enum: [2, 4, 8, 12, 16]



          slew-rate:

            enum: [0, 1]



          mediatek,pull-up-adv:

            description: |

              Pull up setings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.

              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.

            $ref: /schemas/types.yaml#/definitions/uint32

            enum: [0, 1, 2, 3]



          mediatek,pull-down-adv:

            description: |

              Pull down settings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.

              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.

            $ref: /schemas/types.yaml#/definitions/uint32

            enum: [0, 1, 2, 3]



          mediatek,tdsel:

            description: |

              An integer describing the steps for output level shifter duty

              cycle when asserted (high pulse width adjustment). Valid arguments

              are from 0 to 15.

            $ref: /schemas/types.yaml#/definitions/uint32



          mediatek,rdsel:

            description: |

              An integer describing the steps for input level shifter duty cycle

              when asserted (high pulse width adjustment). Valid arguments are

              from 0 to 63.

            $ref: /schemas/types.yaml#/definitions/uint32



        required:

          - pinmux



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/pinctrl/mt6797-pinfunc.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pio: pinctrl@10005000 {

            compatible = "mediatek,mt6797-pinctrl";

            reg = <0 0x10005000 0 0x1000>,

                  <0 0x10002000 0 0x400>,

                  <0 0x10002400 0 0x400>,

                  <0 0x10002800 0 0x400>,

                  <0 0x10002C00 0 0x400>;

            reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt";

            gpio-controller;

            #gpio-cells = <2>;



            uart_pins_a: uart-0 {

                pins1 {

                    pinmux = <MT6797_GPIO232__FUNC_URXD1>,

                            <MT6797_GPIO233__FUNC_UTXD1>;

                };

            };

        };

    };

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -16284,7 +16284,7 @@ M: Sean Wang <sean.wang@kernel.org> 
L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml

F:	Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml

F:	Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml

F:	Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml

F:	Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml

F:	drivers/pinctrl/mediatek/