Unverified Commit 6c62b726 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!5038 [OLK-5.10] Do not serialize MSR accesses on AMD 

Merge Pull Request from: @kile2009 
 
AMD and Hygon do not need to use MFENCE when accessing the APIC and TSC_DEADLINE MSR
backporting the fix from upstream to improve the performance 
 
Link:https://gitee.com/openeuler/kernel/pulls/5038

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarAichun Shi <aichun.shi@intel.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 4fa70990 93cdde8b

arch/x86/include/asm/barrier.h

+0 −18
Original line number Diff line number Diff line
@@ -84,22 +84,4 @@ do { \ 


#include <asm-generic/barrier.h>



/*

 * Make previous memory operations globally visible before

 * a WRMSR.

 *

 * MFENCE makes writes visible, but only affects load/store

 * instructions.  WRMSR is unfortunately not a load/store

 * instruction and is unaffected by MFENCE.  The LFENCE ensures

 * that the WRMSR is not reordered.

 *

 * Most WRMSRs are full serializing instructions themselves and

 * do not require this barrier.  This is only required for the

 * IA32_TSC_DEADLINE and X2APIC MSRs.

 */

static inline void weak_wrmsr_fence(void)

{

	asm volatile("mfence; lfence" : : : "memory");

}



#endif /* _ASM_X86_BARRIER_H */

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -328,6 +328,7 @@ 
#define X86_FEATURE_SRSO		(11*32+24) /* "" AMD BTB untrain RETs */

#define X86_FEATURE_SRSO_ALIAS		(11*32+25) /* "" AMD BTB untrain RETs through aliasing */

#define X86_FEATURE_IBPB_ON_VMEXIT	(11*32+26) /* "" Issue an IBPB only on VMEXIT */

#define X86_FEATURE_APIC_MSRS_FENCE	(11*32+27) /* "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing */



/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

arch/x86/include/asm/processor.h

+18 −0
Original line number Diff line number Diff line
@@ -904,4 +904,22 @@ bool arch_is_platform_page(u64 paddr); 


extern bool gds_ucode_mitigated(void);



/*

 * Make previous memory operations globally visible before

 * a WRMSR.

 *

 * MFENCE makes writes visible, but only affects load/store

 * instructions.  WRMSR is unfortunately not a load/store

 * instruction and is unaffected by MFENCE.  The LFENCE ensures

 * that the WRMSR is not reordered.

 *

 * Most WRMSRs are full serializing instructions themselves and

 * do not require this barrier.  This is only required for the

 * IA32_TSC_DEADLINE and X2APIC MSRs.

 */

static inline void weak_wrmsr_fence(void)

{

	alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE));

}



#endif /* _ASM_X86_PROCESSOR_H */

arch/x86/kernel/cpu/amd.c

+3 −0
Original line number Diff line number Diff line
@@ -1178,6 +1178,9 @@ static void init_amd(struct cpuinfo_x86 *c) 
		pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");

		setup_force_cpu_bug(X86_BUG_DIV0);

	}



	/* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */

	clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);

}



#ifdef CONFIG_X86_32

arch/x86/kernel/cpu/common.c

+7 −0
Original line number Diff line number Diff line
@@ -1708,6 +1708,13 @@ static void identify_cpu(struct cpuinfo_x86 *c) 
	c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);

#endif





	/*

	 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and

	 * Hygon will clear it in ->c_init() below.

	 */

	set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);



	/*

	 * Vendor-specific initialization.  In this section we

	 * canonicalize the feature flags, meaning if there are