Commit 6c5d66cb authored Dec 02, 2021 by Vladimir Oltean Committed by Shawn Guo Dec 14, 2021

arm64: dts: ls1028a-rdb: sort nodes alphabetically by label



In preparation for this board's device tree synchronization with U-Boot,
we must find a common node ordering pattern. Alphabetical sounds about
right.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

parent 44d0dfee

arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts

+42 −42

Original line number	Diff line number	Diff line
		@@ -102,6 +102,48 @@
		};
		};

		&duart0 {
		status = "okay";
		};

		&duart1 {
		status = "okay";
		};

		&enetc_mdio_pf3 {
		sgmii_phy0: ethernet-phy@2 {
		reg = <0x2>;
		};

		/* VSC8514 QSGMII quad PHY */
		qsgmii_phy0: ethernet-phy@10 {
		reg = <0x10>;
		};

		qsgmii_phy1: ethernet-phy@11 {
		reg = <0x11>;
		};

		qsgmii_phy2: ethernet-phy@12 {
		reg = <0x12>;
		};

		qsgmii_phy3: ethernet-phy@13 {
		reg = <0x13>;
		};
		};

		&enetc_port0 {
		phy-handle = <&sgmii_phy0>;
		phy-mode = "sgmii";
		managed = "in-band-status";
		status = "okay";
		};

		&enetc_port2 {
		status = "okay";
		};

		&esdhc {
		sd-uhs-sdr104;
		sd-uhs-sdr50;
		@@ -188,48 +230,6 @@
		};
		};

		&duart0 {
		status = "okay";
		};

		&duart1 {
		status = "okay";
		};

		&enetc_mdio_pf3 {
		sgmii_phy0: ethernet-phy@2 {
		reg = <0x2>;
		};

		/* VSC8514 QSGMII quad PHY */
		qsgmii_phy0: ethernet-phy@10 {
		reg = <0x10>;
		};

		qsgmii_phy1: ethernet-phy@11 {
		reg = <0x11>;
		};

		qsgmii_phy2: ethernet-phy@12 {
		reg = <0x12>;
		};

		qsgmii_phy3: ethernet-phy@13 {
		reg = <0x13>;
		};
		};

		&enetc_port0 {
		phy-handle = <&sgmii_phy0>;
		phy-mode = "sgmii";
		managed = "in-band-status";
		status = "okay";
		};

		&enetc_port2 {
		status = "okay";
		};

		&mscc_felix {
		status = "okay";
		};