Commit 6c528f34 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'platform-drivers-x86-v5.17-4' of... 

Merge tag 'platform-drivers-x86-v5.17-4' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86

Pull more x86 platform driver fixes from Hans de Goede:
 "Two more fixes:

   - Fix suspend/resume regression on AMD Cezanne APUs in >= 5.16

   - Fix Microsoft Surface 3 battery readings"

* tag 'platform-drivers-x86-v5.17-4' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86:
  surface: surface3_power: Fix battery readings on batteries without a serial number
  platform/x86: amd-pmc: Set QOS during suspend on CZN w/ timer wakeup
parents 91318b29 21d90aae

drivers/platform/surface/surface3_power.c

+10 −3
Original line number Diff line number Diff line
@@ -232,14 +232,21 @@ static int mshw0011_bix(struct mshw0011_data *cdata, struct bix *bix) 
	}

	bix->last_full_charg_capacity = ret;



	/* get serial number */

	/*

	 * Get serial number, on some devices (with unofficial replacement

	 * battery?) reading any of the serial number range addresses gets

	 * nacked in this case just leave the serial number empty.

	 */

	ret = i2c_smbus_read_i2c_block_data(client, MSHW0011_BAT0_REG_SERIAL_NO,

					    sizeof(buf), buf);

	if (ret != sizeof(buf)) {

	if (ret == -EREMOTEIO) {

		/* no serial number available */

	} else if (ret != sizeof(buf)) {

		dev_err(&client->dev, "Error reading serial no: %d\n", ret);

		return ret;

	}

	} else {

		snprintf(bix->serial, ARRAY_SIZE(bix->serial), "%3pE%6pE", buf + 7, buf);

	}



	/* get cycle count */

	ret = i2c_smbus_read_word_data(client, MSHW0011_BAT0_REG_CYCLE_CNT);

drivers/platform/x86/amd-pmc.c

+33 −9
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <linux/module.h>

#include <linux/pci.h>

#include <linux/platform_device.h>

#include <linux/pm_qos.h>

#include <linux/rtc.h>

#include <linux/suspend.h>

#include <linux/seq_file.h>
@@ -85,6 +86,9 @@ 
#define PMC_MSG_DELAY_MIN_US		50

#define RESPONSE_REGISTER_LOOP_MAX	20000



/* QoS request for letting CPUs in idle states, but not the deepest */

#define AMD_PMC_MAX_IDLE_STATE_LATENCY	3



#define SOC_SUBSYSTEM_IP_MAX	12

#define DELAY_MIN_US		2000

#define DELAY_MAX_US		3000
@@ -131,6 +135,7 @@ struct amd_pmc_dev { 
	struct device *dev;

	struct pci_dev *rdev;

	struct mutex lock; /* generic mutex lock */

	struct pm_qos_request amd_pmc_pm_qos_req;

#if IS_ENABLED(CONFIG_DEBUG_FS)

	struct dentry *dbgfs_dir;

#endif /* CONFIG_DEBUG_FS */
@@ -521,6 +526,14 @@ static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) 
	rc = rtc_alarm_irq_enable(rtc_device, 0);

	dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);



	/*

	 * Prevent CPUs from getting into deep idle states while sending OS_HINT

	 * which is otherwise generally safe to send when at least one of the CPUs

	 * is not in deep idle states.

	 */

	cpu_latency_qos_update_request(&pdev->amd_pmc_pm_qos_req, AMD_PMC_MAX_IDLE_STATE_LATENCY);

	wake_up_all_idle_cpus();



	return rc;

}
@@ -538,24 +551,31 @@ static int __maybe_unused amd_pmc_suspend(struct device *dev) 
	/* Activate CZN specific RTC functionality */

	if (pdev->cpu_id == AMD_CPU_ID_CZN) {

		rc = amd_pmc_verify_czn_rtc(pdev, &arg);

		if (rc < 0)

			return rc;

		if (rc)

			goto fail;

	}



	/* Dump the IdleMask before we send hint to SMU */

	amd_pmc_idlemask_read(pdev, dev, NULL);

	msg = amd_pmc_get_os_hint(pdev);

	rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);

	if (rc)

	if (rc) {

		dev_err(pdev->dev, "suspend failed\n");

		goto fail;

	}



	if (enable_stb)

		rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);

	if (rc) {

		dev_err(pdev->dev, "error writing to STB\n");

		return rc;

		goto fail;

	}



	return 0;

fail:

	if (pdev->cpu_id == AMD_CPU_ID_CZN)

		cpu_latency_qos_update_request(&pdev->amd_pmc_pm_qos_req,

						PM_QOS_DEFAULT_VALUE);

	return rc;

}
@@ -579,12 +599,15 @@ static int __maybe_unused amd_pmc_resume(struct device *dev) 
	/* Write data incremented by 1 to distinguish in stb_read */

	if (enable_stb)

		rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1);

	if (rc)	{

	if (rc)

		dev_err(pdev->dev, "error writing to STB\n");

		return rc;

	}



	return 0;

	/* Restore the QoS request back to defaults if it was set */

	if (pdev->cpu_id == AMD_CPU_ID_CZN)

		cpu_latency_qos_update_request(&pdev->amd_pmc_pm_qos_req,

						PM_QOS_DEFAULT_VALUE);



	return rc;

}



static const struct dev_pm_ops amd_pmc_pm_ops = {
@@ -722,6 +745,7 @@ static int amd_pmc_probe(struct platform_device *pdev) 
	amd_pmc_get_smu_version(dev);

	platform_set_drvdata(pdev, dev);

	amd_pmc_dbgfs_register(dev);

	cpu_latency_qos_add_request(&dev->amd_pmc_pm_qos_req, PM_QOS_DEFAULT_VALUE);

	return 0;



err_pci_dev_put: