Unverified Commit 6c45b2d6 authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: nau8822: add speaker Bridge Tied Output

Merge series from Francesco Dolcini <francesco@dolcini.it>:

Add support for BTL (Bridge Tied Load) configuration to NAU8822 audio codec,
since this requires adding a new property to the binding convert it from
txt to yaml first.
parents 8c187e22 968b4206
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NAU8822 audio CODEC

This device supports I2C only.

Required properties:

  - compatible : "nuvoton,nau8822"

  - reg : the I2C address of the device.

Example:

codec: nau8822@1a {
	compatible = "nuvoton,nau8822";
	reg = <0x1a>;
};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/nuvoton,nau8822.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NAU8822 audio CODEC

description: |
  24 bit stereo audio codec with speaker driver.
  This device supports I2C/SPI.

maintainers:
  - David Lin <CTLIN0@nuvoton.com>

properties:
  compatible:
    enum:
      - nuvoton,nau8822

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        codec@1a {
            compatible = "nuvoton,nau8822";
            reg = <0x1a>;
        };
    };
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@@ -1056,6 +1056,7 @@ static const int update_reg[] = {
static int nau8822_probe(struct snd_soc_component *component)
{
	int i;
	struct device_node *of_node = component->dev->of_node;

	/*
	 * Set the update bit in all registers, that have one. This way all
@@ -1066,6 +1067,14 @@ static int nau8822_probe(struct snd_soc_component *component)
		snd_soc_component_update_bits(component,
			update_reg[i], 0x100, 0x100);

	/* Check property to configure the two loudspeaker outputs as
	 * a single Bridge Tied Load output
	 */
	if (of_property_read_bool(of_node, "nuvoton,spk-btl"))
		snd_soc_component_update_bits(component,
					      NAU8822_REG_RIGHT_SPEAKER_CONTROL,
					      NAU8822_RSUBBYP, NAU8822_RSUBBYP);

	return 0;
}

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@@ -187,6 +187,15 @@
/* NAU8822_REG_PLL_K3 (0x27) */
#define NAU8822_PLLK3_MASK			0x1FF

/* NAU8822_REG_RIGHT_SPEAKER_CONTROL (0x2B) */
#define NAU8822_RMIXMUT				0x20
#define NAU8822_RSUBBYP				0x10

#define NAU8822_RAUXRSUBG_SFT			1
#define NAU8822_RAUXRSUBG_MASK			0x0E

#define NAU8822_RAUXSMUT			0x01

/* System Clock Source */
enum {
	NAU8822_CLK_MCLK,