Commit 6c3cbaa0 authored by Radhey Shyam Pandey's avatar Radhey Shyam Pandey Committed by Jakub Kicinski
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net: xilinx: axiethernet: Introduce helper functions for MDC enable/disable 



Introduce helper functions to enable/disable MDIO interface clock. This
change serves a preparatory patch for the coming feature to dynamically
control the management bus clock.

Signed-off-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent ad8fc41c

drivers/net/ethernet/xilinx/xilinx_axienet.h

+2 −0
Original line number Diff line number Diff line
@@ -378,6 +378,7 @@ struct axidma_bd { 
 * @dev:	Pointer to device structure

 * @phy_node:	Pointer to device node structure

 * @mii_bus:	Pointer to MII bus structure

 * @mii_clk_div: MII bus clock divider value

 * @regs_start: Resource start for axienet device addresses

 * @regs:	Base address for the axienet_local device address space

 * @dma_regs:	Base address for the axidma device address space
@@ -427,6 +428,7 @@ struct axienet_local { 


	/* MDIO bus data */

	struct mii_bus *mii_bus;	/* MII bus reference */

	u8 mii_clk_div; /* MII bus clock divider value */



	/* IO registers, dma functions and IRQs */

	resource_size_t regs_start;

drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c

+24 −5
Original line number Diff line number Diff line
@@ -30,6 +30,23 @@ static int axienet_mdio_wait_until_ready(struct axienet_local *lp) 
				  1, 20000);

}



/* Enable the MDIO MDC. Called prior to a read/write operation */

static void axienet_mdio_mdc_enable(struct axienet_local *lp)

{

	axienet_iow(lp, XAE_MDIO_MC_OFFSET,

		    ((u32)lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK));

}



/* Disable the MDIO MDC. Called after a read/write operation*/

static void axienet_mdio_mdc_disable(struct axienet_local *lp)

{

	u32 mc_reg;



	mc_reg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);

	axienet_iow(lp, XAE_MDIO_MC_OFFSET,

		    (mc_reg & ~XAE_MDIO_MC_MDIOEN_MASK));

}



/**

 * axienet_mdio_read - MDIO interface read function

 * @bus:	Pointer to mii bus structure
@@ -124,7 +141,9 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg, 
 **/

int axienet_mdio_enable(struct axienet_local *lp)

{

	u32 clk_div, host_clock;

	u32 host_clock;



	lp->mii_clk_div = 0;



	if (lp->clk) {

		host_clock = clk_get_rate(lp->clk);
@@ -176,19 +195,19 @@ int axienet_mdio_enable(struct axienet_local *lp) 
	 * "clock-frequency" from the CPU

	 */



	clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;

	lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;

	/* If there is any remainder from the division of

	 * fHOST / (MAX_MDIO_FREQ * 2), then we need to add

	 * 1 to the clock divisor or we will surely be above 2.5 MHz

	 */

	if (host_clock % (MAX_MDIO_FREQ * 2))

		clk_div++;

		lp->mii_clk_div++;



	netdev_dbg(lp->ndev,

		   "Setting MDIO clock divisor to %u/%u Hz host clock.\n",

		   clk_div, host_clock);

		   lp->mii_clk_div, host_clock);



	axienet_iow(lp, XAE_MDIO_MC_OFFSET, clk_div | XAE_MDIO_MC_MDIOEN_MASK);

	axienet_iow(lp, XAE_MDIO_MC_OFFSET, lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK);



	return axienet_mdio_wait_until_ready(lp);

}