Commit 6c389328 authored by Hou Zhiqiang's avatar Hou Zhiqiang Committed by Lorenzo Pieralisi
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dt-bindings: pci: layerscape-pci: Add a optional property big-endian 

This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.

Link: https://lore.kernel.org/r/20220311234938.8706-2-leoyang.li@nxp.com


Signed-off-by: default avatarHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
parent 31231092

Documentation/devicetree/bindings/pci/layerscape-pci.txt

+4 −0
Original line number Diff line number Diff line
@@ -40,6 +40,10 @@ Required properties: 
  of the data transferred from/to the IP block. This can avoid the software

  cache flush/invalid actions, and improve the performance significantly.



Optional properties:

- big-endian: If the PEX_LUT and PF register block is in big-endian, specify

  this property.



Example:



	pcie@3400000 {