Commit 6c119330 authored by Conor Dooley's avatar Conor Dooley
Browse files

riscv: dts: microchip: update memory configuration for v2022.10 



In the v2022.10 reference design, the seg registers are going to be
changed, resulting in a required change to the memory map in Linux.
A small 4M reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload.bin between
reboots of a specific context.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent d4916664

arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts

+13 −2
Original line number Diff line number Diff line
@@ -33,15 +33,26 @@ 


	ddrc_cache_lo: memory@80000000 {

		device_type = "memory";

		reg = <0x0 0x80000000 0x0 0x2e000000>;

		reg = <0x0 0x80000000 0x0 0x40000000>;

		status = "okay";

	};



	ddrc_cache_hi: memory@1000000000 {

		device_type = "memory";

		reg = <0x10 0x0 0x0 0x40000000>;

		reg = <0x10 0x40000000 0x0 0x40000000>;

		status = "okay";

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		hss_payload: region@BFC00000 {

			reg = <0x0 0xBFC00000 0x0 0x400000>;

			no-map;

		};

	};

};



&core_pwm0 {