Commit 6c0afc57 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools headers UAPI: Update tools' copy of linux/coresight-pmu.h 



To get the changes in these commits:

  88f11864 ("coresight: etm-perf: Support PID tracing for kernel at EL2")
  53abf3fe ("coresight: etm-perf: Clarify comment on perf options")

This will possibly be used in patches lined up for v5.13.

And silence this perf build warning:

  Warning: Kernel ABI header at 'tools/include/linux/coresight-pmu.h' differs from latest version at 'include/linux/coresight-pmu.h'
  diff -u tools/include/linux/coresight-pmu.h include/linux/coresight-pmu.h

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 743108e1

tools/include/linux/coresight-pmu.h

+15 −5
Original line number Diff line number Diff line
@@ -10,17 +10,27 @@ 
#define CORESIGHT_ETM_PMU_NAME "cs_etm"

#define CORESIGHT_ETM_PMU_SEED  0x10



/* ETMv3.5/PTM's ETMCR config bit */

/*

 * Below are the definition of bit offsets for perf option, and works as

 * arbitrary values for all ETM versions.

 *

 * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore,

 * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and

 * directly use below macros as config bits.

 */

#define ETM_OPT_CYCACC		12

#define ETM_OPT_CTXTID		14

#define ETM_OPT_CTXTID2		15

#define ETM_OPT_TS		28

#define ETM_OPT_RETSTK		29



/* ETMv4 CONFIGR programming bits for the ETM OPTs */

#define ETM4_CFG_BIT_CYCACC	4

#define ETM4_CFG_BIT_CTXTID	6

#define ETM4_CFG_BIT_VMID	7

#define ETM4_CFG_BIT_TS		11

#define ETM4_CFG_BIT_RETSTK	12

#define ETM4_CFG_BIT_VMID_OPT	15



static inline int coresight_get_trace_id(int cpu)

{