Unverified Commit 6c06ad34 authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown
Browse files

ASoC: dt-bindings: fsl-sai: Add two PLL clock source 



Add two PLL clock source, they are the parent clocks of root clock
one is for 8kHz series rates, another one is for 11kHz series rates.
They are optional clocks, if there are such clocks, then driver
can switch between them for supporting more accurate rates.

Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1656667961-1799-7-git-send-email-shengjiu.wang@nxp.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent df0835a8

Documentation/devicetree/bindings/sound/fsl-sai.txt

+3 −0
Original line number Diff line number Diff line
@@ -21,6 +21,9 @@ Required properties: 
  - clock-names		: Must include the "bus" for register access and

			  "mclk1", "mclk2", "mclk3" for bit clock and frame

			  clock providing.

                          "pll8k", "pll11k" are optional, they are the clock

                          source for root clock, one is for 8kHz series rates

                          another one is for 11kHz series rates.

  - dmas		: Generic dma devicetree binding as described in

			  Documentation/devicetree/bindings/dma/dma.txt.