Commit 6bad4ff8 authored by David Zhang's avatar David Zhang Committed by Alex Deucher
Browse files

drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support 



[why & how]

Expose vendor specific DPCD registers for rate controlling the eDP sink
TCON's refresh rate during PSR active. When used in combination with
PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for
short.

v2: Add all DPCD registers required

Signed-off-by: default avatarDavid Zhang <dingchen.zhang@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 44961f6e

drivers/gpu/drm/amd/display/include/ddc_service_types.h

+4 −0
Original line number Diff line number Diff line
@@ -41,6 +41,10 @@ 
#define DP_DEVICE_ID_38EC11 0x38EC11

#define DP_FORCE_PSRSU_CAPABILITY 0x40F



#define DP_SINK_PSR_ACTIVE_VTOTAL		0x373

#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE	0x375

#define DP_SOURCE_PSR_ACTIVE_VTOTAL		0x376



enum ddc_result {

	DDC_RESULT_UNKNOWN = 0,

	DDC_RESULT_SUCESSFULL,