Unverified Commit 6b76bcc0 authored by Sugar Zhang's avatar Sugar Zhang Committed by Mark Brown
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ASoC: rockchip: i2s: Fixup clk div error 



MCLK maybe not precise as required because of PLL,
but which still can be used and no side effect. so,
using DIV_ROUND_CLOSEST instead div.

e.g.

set mclk to 11289600 Hz, but get 11289598 Hz.

Signed-off-by: default avatarSugar Zhang <sugar.zhang@rock-chips.com>
Link: https://lore.kernel.org/r/1629950520-14190-2-git-send-email-sugar.zhang@rock-chips.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent ebfea671

sound/soc/rockchip/rockchip_i2s.c

+2 −2
Original line number Diff line number Diff line
@@ -280,10 +280,10 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, 
	if (i2s->is_master_mode) {

		mclk_rate = clk_get_rate(i2s->mclk);

		bclk_rate = i2s->bclk_ratio * params_rate(params);

		if (bclk_rate == 0 || mclk_rate % bclk_rate)

		if (!bclk_rate)

			return -EINVAL;



		div_bclk = mclk_rate / bclk_rate;

		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);

		div_lrck = bclk_rate / params_rate(params);

		regmap_update_bits(i2s->regmap, I2S_CKR,

				   I2S_CKR_MDIV_MASK,