Commit 6b629f28 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'for-3.20' of... 

Merge tag 'for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-testing

Kishon writes:

Adds a new Rockchip PHY driver and contains miscellaneous fixes.
parents dd321740 bbd3ce86

Documentation/devicetree/bindings/phy/phy-miphy28lp.txt

+16 −27
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ Required properties (port (child) node): 
		  filled in "reg". It can also contain the offset of the system configuration

		  registers used as glue-logic to setup the device for SATA/PCIe or USB3

		  devices.

- st,syscfg	: Offset of the parent configuration register.

- resets	: phandle to the parent reset controller.

- reset-names	: Associated name must be "miphy-sw-rst".
@@ -54,18 +55,12 @@ example: 
			phy_port0: port@9b22000 {

				reg = <0x9b22000 0xff>,

				      <0x9b09000 0xff>,

				      <0x9b04000 0xff>,

				      <0x114 0x4>, /* sysctrl MiPHY cntrl */

				      <0x818 0x4>, /* sysctrl MiPHY status*/

				      <0xe0  0x4>, /* sysctrl PCIe */

				      <0xec  0x4>; /* sysctrl SATA */

				      <0x9b04000 0xff>;

				reg-names = "sata-up",

					    "pcie-up",

					    "pipew",

					    "miphy-ctrl-glue",

					    "miphy-status-glue",

					    "pcie-glue",

					    "sata-glue";

					    "pipew";



				st,syscfg = <0x114 0x818 0xe0 0xec>;

				#phy-cells = <1>;

				st,osc-rdy;

				reset-names = "miphy-sw-rst";
@@ -75,18 +70,13 @@ example: 
			phy_port1: port@9b2a000 {

				reg = <0x9b2a000 0xff>,

				      <0x9b19000 0xff>,

				      <0x9b14000 0xff>,

				      <0x118 0x4>,

				      <0x81c 0x4>,

				      <0xe4  0x4>,

				      <0xf0  0x4>;

				      <0x9b14000 0xff>;

				reg-names = "sata-up",

					    "pcie-up",

					    "pipew",

					    "miphy-ctrl-glue",

					    "miphy-status-glue",

					    "pcie-glue",

					    "sata-glue";

					    "pipew";



				st,syscfg = <0x118 0x81c 0xe4 0xf0>;



				#phy-cells = <1>;

				st,osc-force-ext;

				reset-names = "miphy-sw-rst";
@@ -95,13 +85,12 @@ example: 


			phy_port2: port@8f95000 {

				reg = <0x8f95000 0xff>,

				      <0x8f90000 0xff>,

				      <0x11c 0x4>,

				      <0x820 0x4>;

				      <0x8f90000 0xff>;

				reg-names = "pipew",

				    "usb3-up",

				    "miphy-ctrl-glue",

				    "miphy-status-glue";

					    "usb3-up";



				st,syscfg = <0x11c 0x820>;



				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
@@ -125,4 +114,4 @@ example: 


Macro definitions for the supported miphy configuration can be found in:



include/dt-bindings/phy/phy-miphy28lp.h
 
include/dt-bindings/phy/phy.h

Documentation/devicetree/bindings/phy/phy-miphy365x.txt

+8 −7
Original line number Diff line number Diff line
@@ -6,8 +6,10 @@ for SATA and PCIe. 


Required properties (controller (parent) node):

- compatible    : Should be "st,miphy365x-phy"

- st,syscfg     : Should be a phandle of the system configuration register group

		  which contain the SATA, PCIe mode setting bits

- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group

		  containing the miphy registers and integer array should contain

		  an entry for each port sub-node, specifying the control

		  register offset inside the sysconfig group.



Required nodes	:  A sub-node is required for each channel the controller

		   provides. Address range information including the usual
@@ -26,7 +28,6 @@ Required properties (port (child) node): 
		  registers filled in "reg":

			- sata:   For SATA devices

			- pcie:   For PCIe devices

			- syscfg: To specify the syscfg based config register



Optional properties (port (child) node):

- st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
@@ -39,20 +40,20 @@ Example: 


	miphy365x_phy: miphy365x@fe382000 {

		compatible      = "st,miphy365x-phy";

		st,syscfg  	= <&syscfg_rear>;

		st,syscfg  	= <&syscfg_rear 0x824 0x828>;

		#address-cells	= <1>;

		#size-cells	= <1>;

		ranges;



		phy_port0: port@fe382000 {

			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;

			reg-names = "sata", "pcie", "syscfg";

			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;

			reg-names = "sata", "pcie";

			#phy-cells = <1>;

			st,sata-gen = <3>;

		};



		phy_port1: port@fe38a000 {

			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;

			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;

			reg-names = "sata", "pcie", "syscfg";

			#phy-cells = <1>;

			st,pcie-tx-pol-inv;

Documentation/devicetree/bindings/phy/phy-stih407-usb.txt

+2 −8
Original line number Diff line number Diff line
@@ -5,10 +5,7 @@ host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC fa 


Required properties:

- compatible		: should be "st,stih407-usb2-phy"

- reg			: contain the offset and length of the system configuration registers

			  used as glue logic to control & parameter phy

- reg-names		: the names of the system configuration registers in "reg", should be "param" and "reg"

- st,syscfg		: sysconfig register to manage phy parameter at driver level

- st,syscfg		: phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets

- resets		: list of phandle and reset specifier pairs. There should be two entries, one

			  for the whole phy and one for the port

- reset-names		: list of reset signal names. Should be "global" and "port"
@@ -19,11 +16,8 @@ Example: 


usb2_picophy0: usbpicophy@f8 {

	compatible	= "st,stih407-usb2-phy";

	reg		= <0xf8 0x04>,	/* syscfg 5062 */

			  <0xf4 0x04>;	/* syscfg 5061 */

	reg-names	= "param", "ctrl";

	#phy-cells	= <0>;

	st,syscfg	= <&syscfg_core>;

	st,syscfg	= <&syscfg_core 0x100 0xf4>;

	resets		= <&softreset STIH407_PICOPHY_SOFTRESET>,

			  <&picophyreset STIH407_PICOPHY0_RESET>;

	reset-names	= "global", "port";

Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt

0 → 100644
+37 −0
Original line number Diff line number Diff line 
ROCKCHIP USB2 PHY



Required properties:

 - compatible: rockchip,rk3288-usb-phy

 - rockchip,grf : phandle to the syscon managing the "general

   register files"

 - #address-cells: should be 1

 - #size-cells: should be 0



Sub-nodes:

Each PHY should be represented as a sub-node.



Sub-nodes

required properties:

- #phy-cells: should be 0

- reg: PHY configure reg address offset in GRF

		"0x320" - for PHY attach to OTG controller

		"0x334" - for PHY attach to HOST0 controller

		"0x348" - for PHY attach to HOST1 controller



Optional Properties:

- clocks : phandle + clock specifier for the phy clocks

- clock-names: string, clock name, must be "phyclk"



Example:



usbphy: phy {

	compatible = "rockchip,rk3288-usb-phy";

	rockchip,grf = <&grf>;

	#address-cells = <1>;

	#size-cells = <0>;



	usbphy0: usb-phy0 {

		#phy-cells = <0>;

		reg = <0x320>;

	};

};

Documentation/devicetree/bindings/phy/samsung-phy.txt

+1 −1
Original line number Diff line number Diff line
@@ -3,8 +3,8 @@ Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY 


Required properties:

- compatible : should be "samsung,s5pv210-mipi-video-phy";

- reg : offset and length of the MIPI DPHY register set;

- #phy-cells : from the generic phy bindings, must be 1;

- syscon - phandle to the PMU system controller;



For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in

the PHY specifier identifies the PHY and its meaning is as follows: