Unverified Commit 6b533828 authored by Greentime Hu's avatar Greentime Hu Committed by Palmer Dabbelt
Browse files

riscv: Clear vector regfile on bootup 



clear vector registers on boot if kernel supports V.

Signed-off-by: default avatarGreentime Hu <greentime.hu@sifive.com>
Signed-off-by: default avatarVineet Gupta <vineetg@rivosinc.com>
Signed-off-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230605110724.21391-6-andy.chiu@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent b5665d2a

arch/riscv/kernel/head.S

+25 −2
Original line number Diff line number Diff line
@@ -392,7 +392,7 @@ ENTRY(reset_regs) 
#ifdef CONFIG_FPU

	csrr	t0, CSR_MISA

	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)

	beqz	t0, .Lreset_regs_done

	beqz	t0, .Lreset_regs_done_fpu



	li	t1, SR_FS

	csrs	CSR_STATUS, t1
@@ -430,8 +430,31 @@ ENTRY(reset_regs) 
	fmv.s.x	f31, zero

	csrw	fcsr, 0

	/* note that the caller must clear SR_FS */

.Lreset_regs_done_fpu:

#endif /* CONFIG_FPU */

.Lreset_regs_done:



#ifdef CONFIG_RISCV_ISA_V

	csrr	t0, CSR_MISA

	li	t1, COMPAT_HWCAP_ISA_V

	and	t0, t0, t1

	beqz	t0, .Lreset_regs_done_vector



	/*

	 * Clear vector registers and reset vcsr

	 * VLMAX has a defined value, VLEN is a constant,

	 * and this form of vsetvli is defined to set vl to VLMAX.

	 */

	li	t1, SR_VS

	csrs	CSR_STATUS, t1

	csrs	CSR_VCSR, x0

	vsetvli t1, x0, e8, m8, ta, ma

	vmv.v.i v0, 0

	vmv.v.i v8, 0

	vmv.v.i v16, 0

	vmv.v.i v24, 0

	/* note that the caller must clear SR_VS */

.Lreset_regs_done_vector:

#endif /* CONFIG_RISCV_ISA_V */

	ret

END(reset_regs)

#endif /* CONFIG_RISCV_M_MODE */