Commit 6b22ef25 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
Browse files

drm/amdgpu: configure the doorbell settings for sdma on non-AID0 



Configure the sdma doorbell settings on NBIF0 and SYSHUB of each AID

v2: fetch aid_id from amdgpu_sdma_instance (Lijo)

Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Acked-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0c552ed3

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

+56 −9
Original line number Diff line number Diff line
@@ -62,10 +62,23 @@ static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev) 
	return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);

}



#define S2A_DOORBELL_REG_LSD_OFFSET	0x40



/* Temporarily add 2 macros below. Range is 0 ~ 3 as total AID number is 4.

 * They will be obsoleted after the latest ip offset header

 * is imported in driver in near future.

 */

#define AMDGPU_SMN_TARGET_AID(x)	((u64)(x) << 32)

#define AMDGPU_SMN_CROSS_AID		(1ULL << 34)



static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance,

			bool use_doorbell, int doorbell_index, int doorbell_size)

{

	u32 doorbell_range = 0, doorbell_ctrl = 0;

	int aid_id = adev->sdma.instance[instance].aid_id;



	if (use_doorbell == false)

		return;



	doorbell_range =

		REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
@@ -80,9 +93,10 @@ static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instan 
		REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,

			S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size);



	switch (instance) {

	switch (instance % adev->sdma.num_inst_per_aid) {

	case 0:

		WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1, doorbell_range);

		WREG32(SOC15_REG_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1) +

			4 * aid_id, doorbell_range);



		doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

					S2A_DOORBELL_ENTRY_1_CTRL,
@@ -94,10 +108,15 @@ static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instan 
					S2A_DOORBELL_ENTRY_1_CTRL,

					S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,

					0x1);

		WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL, doorbell_ctrl);

		WREG32_PCIE_EXT((SOC15_REG_OFFSET(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL)

			+ S2A_DOORBELL_REG_LSD_OFFSET) * 4

			+ AMDGPU_SMN_TARGET_AID(aid_id)

			+ AMDGPU_SMN_CROSS_AID * !!aid_id,

			doorbell_ctrl);

		break;

	case 1:

		WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2, doorbell_range);

		WREG32(SOC15_REG_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2) +

			4 * aid_id, doorbell_range);



		doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

					S2A_DOORBELL_ENTRY_1_CTRL,
@@ -109,10 +128,15 @@ static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instan 
					S2A_DOORBELL_ENTRY_1_CTRL,

					S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,

					0x2);

		WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL, doorbell_ctrl);

		WREG32_PCIE_EXT((SOC15_REG_OFFSET(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL)

			+ S2A_DOORBELL_REG_LSD_OFFSET) * 4

			+ AMDGPU_SMN_TARGET_AID(aid_id)

			+ AMDGPU_SMN_CROSS_AID * !!aid_id,

			doorbell_ctrl);

		break;

	case 2:

		WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3, doorbell_range);

		WREG32(SOC15_REG_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3) +

			4 * aid_id, doorbell_range);



		doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

					S2A_DOORBELL_ENTRY_1_CTRL,
@@ -124,10 +148,22 @@ static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instan 
					S2A_DOORBELL_ENTRY_1_CTRL,

					S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,

					0x8);

		WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL, doorbell_ctrl);

		if (aid_id != 0)

			WREG32_PCIE_EXT((SOC15_REG_OFFSET(NBIO, 0,

				regS2A_DOORBELL_ENTRY_3_CTRL)

				+ S2A_DOORBELL_REG_LSD_OFFSET) * 4

				+ AMDGPU_SMN_TARGET_AID(aid_id)

				+ AMDGPU_SMN_CROSS_AID * !!aid_id,

				doorbell_ctrl);

		else

			WREG32(SOC15_REG_OFFSET(NBIO, 0,

				regS2A_DOORBELL_ENTRY_5_CTRL)

				+ S2A_DOORBELL_REG_LSD_OFFSET,

				doorbell_ctrl);

		break;

	case 3:

		WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4, doorbell_range);

		WREG32(SOC15_REG_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4) +

			4 * aid_id, doorbell_range);



		doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

					S2A_DOORBELL_ENTRY_1_CTRL,
@@ -139,7 +175,18 @@ static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instan 
					S2A_DOORBELL_ENTRY_1_CTRL,

					S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,

					0x9);

		WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_6_CTRL, doorbell_ctrl);

		if (aid_id != 0)

			WREG32_PCIE_EXT((SOC15_REG_OFFSET(NBIO, 0,

				regS2A_DOORBELL_ENTRY_4_CTRL)

				+ S2A_DOORBELL_REG_LSD_OFFSET) * 4

				+ AMDGPU_SMN_TARGET_AID(aid_id)

				+ AMDGPU_SMN_CROSS_AID * !!aid_id,

				doorbell_ctrl);

		else

			WREG32(SOC15_REG_OFFSET(NBIO, 0,

				regS2A_DOORBELL_ENTRY_6_CTRL)

				+ S2A_DOORBELL_REG_LSD_OFFSET,

				doorbell_ctrl);

		break;

	default:

		break;