Commit 6af0a549 authored by Grygorii Strashko's avatar Grygorii Strashko Committed by Tony Lindgren
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ARM: dts: dra7: fix cpsw mdio fck clock 



The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0)
is specified incorrectly, which is caused incorrect MDIO bus clock
configuration MDCLK. The correct CPSW MDIO functional clock is
gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it.

Fixes: 1faa415c ("ARM: dts: Add fck for cpsw mdio for omap variants")
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent e415e4d2

arch/arm/boot/dts/dra7-l4.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -3065,7 +3065,7 @@ 


				davinci_mdio: mdio@1000 {

					compatible = "ti,cpsw-mdio","ti,davinci_mdio";

					clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;

					clocks = <&gmac_main_clk>;

					clock-names = "fck";

					#address-cells = <1>;

					#size-cells = <0>;