Commit 6aec3bfe authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'coresight-next-v5.18-v2' of... 

Merge tag 'coresight-next-v5.18-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux

 into char-misc-next

Suzuki writes:

coresight: changes for v5.18

The coresight update for v5.18 includes
  - TRBE erratum workarounds for Arm Cortex-A510
  - Fixes for leaking root namespace PIDs into non-root namespace
    trace sessions
  - Miscellaneous fixes and cleanups

Updated tag to reflect missing committer s-o-b tags.

Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>

* tag 'coresight-next-v5.18-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux:
  coresight: Drop unused 'none' enum value for each component
  coresight: etm3x: Don't trace PID for non-root PID namespace
  coresight: etm4x: Don't trace PID for non-root PID namespace
  coresight: etm4x: Don't use virtual contextID for non-root PID namespace
  coresight: etm4x: Add lock for reading virtual context ID comparator
  coresight: trbe: Move check for kernel page table isolation from EL0 to probe
  coresight: no-op refactor to make INSTP0 check more idiomatic
  hwtracing: coresight: Replace acpi_bus_get_device()
  coresight: syscfg: Fix memleak on registration failure in cscfg_create_device
  coresight: Fix TRCCONFIGR.QE sysfs interface
  coresight: trbe: Work around the trace data corruption
  coresight: trbe: Work around the invalid prohibited states
  coresight: trbe: Work around the ignored system register writes
parents cc6ce5ac 286f9505

arch/arm64/Kconfig

+3 −3
Original line number Diff line number Diff line
@@ -807,7 +807,7 @@ config ARM64_ERRATUM_2224489 


config ARM64_ERRATUM_2064142

	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	depends on CORESIGHT_TRBE

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.
@@ -825,7 +825,7 @@ config ARM64_ERRATUM_2064142 


config ARM64_ERRATUM_2038923

	bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	depends on CORESIGHT_TRBE

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 2038923.
@@ -848,7 +848,7 @@ config ARM64_ERRATUM_2038923 


config ARM64_ERRATUM_1902691

	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	depends on CORESIGHT_TRBE

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.

drivers/hwtracing/coresight/coresight-core.c

+0 −3
Original line number Diff line number Diff line
@@ -1278,9 +1278,6 @@ static struct attribute *coresight_source_attrs[] = { 
ATTRIBUTE_GROUPS(coresight_source);



static struct device_type coresight_dev_type[] = {

	{

		.name = "none",

	},

	{

		.name = "sink",

		.groups = coresight_sink_groups,

drivers/hwtracing/coresight/coresight-etm3x-core.c

+4 −0
Original line number Diff line number Diff line
@@ -340,6 +340,10 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, 


	config->ctrl = attr->config;



	/* Don't trace contextID when runs in non-root PID namespace */

	if (!task_is_in_init_pid_ns(current))

		config->ctrl &= ~ETMCR_CTXID_SIZE;



	/*

	 * Possible to have cores with PTM (supports ret stack) and ETM

	 * (never has ret stack) on the same SoC. So if we have a request

drivers/hwtracing/coresight/coresight-etm4x-core.c

+9 −3
Original line number Diff line number Diff line
@@ -656,7 +656,9 @@ static int etm4_parse_event_config(struct coresight_device *csdev, 
		config->cfg |= BIT(11);

	}



	if (attr->config & BIT(ETM_OPT_CTXTID))

	/* Only trace contextID when runs in root PID namespace */

	if ((attr->config & BIT(ETM_OPT_CTXTID)) &&

	    task_is_in_init_pid_ns(current))

		/* bit[6], Context ID tracing bit */

		config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
@@ -670,7 +672,11 @@ static int etm4_parse_event_config(struct coresight_device *csdev, 
			ret = -EINVAL;

			goto out;

		}

		config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT);



		/* Only trace virtual contextID when runs in root PID namespace */

		if (task_is_in_init_pid_ns(current))

			config->cfg |= BIT(ETM4_CFG_BIT_VMID) |

				       BIT(ETM4_CFG_BIT_VMID_OPT);

	}



	/* return stack - enable if selected and supported */
@@ -1091,7 +1097,7 @@ static void etm4_init_arch_data(void *info) 
	etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);



	/* INSTP0, bits[2:1] P0 tracing support field */

	if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))

	if (BMVAL(etmidr0, 1, 2) == 0b11)

		drvdata->instrp0 = true;

	else

		drvdata->instrp0 = false;

drivers/hwtracing/coresight/coresight-etm4x-sysfs.c

+36 −2
Original line number Diff line number Diff line
@@ -367,8 +367,12 @@ static ssize_t mode_store(struct device *dev, 
	mode = ETM_MODE_QELEM(config->mode);

	/* start by clearing QE bits */

	config->cfg &= ~(BIT(13) | BIT(14));

	/* if supported, Q elements with instruction counts are enabled */

	if ((mode & BIT(0)) && (drvdata->q_support & BIT(0)))

	/*

	 * if supported, Q elements with instruction counts are enabled.

	 * Always set the low bit for any requested mode. Valid combos are

	 * 0b00, 0b01 and 0b11.

	 */

	if (mode && drvdata->q_support)

		config->cfg |= BIT(13);

	/*

	 * if supported, Q elements with and without instruction
@@ -2111,7 +2115,16 @@ static ssize_t vmid_val_show(struct device *dev, 
	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);

	struct etmv4_config *config = &drvdata->config;



	/*

	 * Don't use virtual contextID tracing if coming from a PID namespace.

	 * See comment in ctxid_pid_store().

	 */

	if (!task_is_in_init_pid_ns(current))

		return -EINVAL;



	spin_lock(&drvdata->spinlock);

	val = (unsigned long)config->vmid_val[config->vmid_idx];

	spin_unlock(&drvdata->spinlock);

	return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);

}
@@ -2123,6 +2136,13 @@ static ssize_t vmid_val_store(struct device *dev, 
	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);

	struct etmv4_config *config = &drvdata->config;



	/*

	 * Don't use virtual contextID tracing if coming from a PID namespace.

	 * See comment in ctxid_pid_store().

	 */

	if (!task_is_in_init_pid_ns(current))

		return -EINVAL;



	/*

	 * only implemented when vmid tracing is enabled, i.e. at least one

	 * vmid comparator is implemented and at least 8 bit vmid size
@@ -2146,6 +2166,13 @@ static ssize_t vmid_masks_show(struct device *dev, 
	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);

	struct etmv4_config *config = &drvdata->config;



	/*

	 * Don't use virtual contextID tracing if coming from a PID namespace.

	 * See comment in ctxid_pid_store().

	 */

	if (!task_is_in_init_pid_ns(current))

		return -EINVAL;



	spin_lock(&drvdata->spinlock);

	val1 = config->vmid_mask0;

	val2 = config->vmid_mask1;
@@ -2163,6 +2190,13 @@ static ssize_t vmid_masks_store(struct device *dev, 
	struct etmv4_config *config = &drvdata->config;

	int nr_inputs;



	/*

	 * Don't use virtual contextID tracing if coming from a PID namespace.

	 * See comment in ctxid_pid_store().

	 */

	if (!task_is_in_init_pid_ns(current))

		return -EINVAL;



	/*

	 * only implemented when vmid tracing is enabled, i.e. at least one

	 * vmid comparator is implemented and at least 8 bit vmid size