Commit 6ad69e07 authored by Michael Walle's avatar Michael Walle Committed by Claudiu Beznea
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ARM: dts: lan966x: add MIIM nodes 



Add the MDIO controller nodes. The integrated PHYs are connected to the
second controller. This controller also takes care of the resets of the
integrated PHYs, thus it has two memory regions. The first controller
is routed to the external MDIO/MDC pins.

By default, they are disabled.

Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: default avatarHoratiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-10-michael@walle.cc


Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
parent 63f29594

arch/arm/boot/dts/lan966x.dtsi

+31 −0
Original line number Diff line number Diff line
@@ -418,6 +418,37 @@ 
			#interrupt-cells = <2>;

		};



		mdio0: mdio@e2004118 {

			compatible = "microchip,lan966x-miim";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0xe2004118 0x24>;

			clocks = <&sys_clk>;

			status = "disabled";

		};



		mdio1: mdio@e200413c {

			compatible = "microchip,lan966x-miim";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0xe200413c 0x24>,

			      <0xe2010020 0x4>;

			clocks = <&sys_clk>;

			status = "disabled";



			phy0: ethernet-phy@1 {

				reg = <1>;

				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

			};



			phy1: ethernet-phy@2 {

				reg = <2>;

				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

			};

		};



		sgpio: gpio@e2004190 {

			compatible = "microchip,sparx5-sgpio";

			reg = <0xe2004190 0x118>;