Commit 6aa5b46d authored by Tinghan Shen's avatar Tinghan Shen Committed by Matthias Brugger
Browse files

arm64: dts: mt8195: Add vdosys and vppsys clock nodes 



Add display clock nodes.

Signed-off-by: default avatarTinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220811025813.21492-12-tinghan.shen@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent e39e72cf

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -983,6 +983,12 @@ 
			#clock-cells = <1>;

		};



		vppsys0: clock-controller@14000000 {

			compatible = "mediatek,mt8195-vppsys0";

			reg = <0 0x14000000 0 0x1000>;

			#clock-cells = <1>;

		};



		wpesys: clock-controller@14e00000 {

			compatible = "mediatek,mt8195-wpesys";

			reg = <0 0x14e00000 0 0x1000>;
@@ -1001,6 +1007,12 @@ 
			#clock-cells = <1>;

		};



		vppsys1: clock-controller@14f00000 {

			compatible = "mediatek,mt8195-vppsys1";

			reg = <0 0x14f00000 0 0x1000>;

			#clock-cells = <1>;

		};



		imgsys: clock-controller@15000000 {

			compatible = "mediatek,mt8195-imgsys";

			reg = <0 0x15000000 0 0x1000>;
@@ -1108,5 +1120,17 @@ 
			reg = <0 0x1b000000 0 0x1000>;

			#clock-cells = <1>;

		};



		vdosys0: syscon@1c01a000 {

			compatible = "mediatek,mt8195-mmsys", "syscon";

			reg = <0 0x1c01a000 0 0x1000>;

			#clock-cells = <1>;

		};



		vdosys1: syscon@1c100000 {

			compatible = "mediatek,mt8195-mmsys", "syscon";

			reg = <0 0x1c100000 0 0x1000>;

			#clock-cells = <1>;

		};

	};

};