Commit 6a92916d authored by Zhengjun Xing's avatar Zhengjun Xing Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update event list for Sapphirerapids 

Update JSON event list for Sapphirerapids to perf.

Based on JSON list v1.02:

https://download.01.org/perfmon/SPR/



Signed-off-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220607092749.1976878-2-zhengjun.xing@linux.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 5fa2481c

tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json

+81 −8
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "L1D.HWPF_MISS",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x51",

        "EventName": "L1D.HWPF_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x20"

    },

    {

        "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",

        "CollectPEBSRecord": "2",
@@ -8,6 +19,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -19,6 +31,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -32,6 +45,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -42,6 +56,7 @@ 
        "EventName": "L1D_PEND_MISS.L2_STALL",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x4"

    },

    {
@@ -53,6 +68,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x4"

    },

    {
@@ -64,6 +80,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -76,6 +93,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -87,6 +105,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1f"

    },

    {
@@ -97,6 +116,7 @@ 
        "EventName": "L2_LINES_OUT.NON_SILENT",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -108,17 +128,19 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "All L2 requests.[This event is alias to L2_RQSTS.REFERENCES]",

        "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_REQUEST.ALL",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts all L2 requests.[This event is alias to L2_RQSTS.REFERENCES]",

        "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.REFERENCES]",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xff"

    },

    {
@@ -130,6 +152,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.MISS]",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x3f"

    },

    {
@@ -141,17 +164,19 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of L2 code requests.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xe4"

    },

    {

        "BriefDescription": "Demand Data Read requests",

        "BriefDescription": "Demand Data Read access L2 cache",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",

        "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xe1"

    },

    {
@@ -163,6 +188,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts demand requests that miss L2 cache.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x27"

    },

    {
@@ -174,8 +200,20 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts demand requests to L2 cache.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xe7"

    },

    {

        "BriefDescription": "L2_RQSTS.ALL_HWPF",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.ALL_HWPF",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xf0"

    },

    {

        "BriefDescription": "RFO requests to L2 cache",

        "CollectPEBSRecord": "2",
@@ -185,6 +223,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xe2"

    },

    {
@@ -196,6 +235,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xc4"

    },

    {
@@ -207,6 +247,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts L2 cache misses when fetching instructions.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x24"

    },

    {
@@ -218,19 +259,32 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xc1"

    },

    {

        "BriefDescription": "Demand Data Read miss L2, no rejects",

        "BriefDescription": "Demand Data Read miss L2 cache",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",

        "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x21"

    },

    {

        "BriefDescription": "L2_RQSTS.HWPF_MISS",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.HWPF_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x30"

    },

    {

        "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]",

        "CollectPEBSRecord": "2",
@@ -240,17 +294,19 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.MISS]",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x3f"

    },

    {

        "BriefDescription": "All L2 requests.[This event is alias to L2_REQUEST.ALL]",

        "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3",

        "EventCode": "0x24",

        "EventName": "L2_RQSTS.REFERENCES",

        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts all L2 requests.[This event is alias to L2_REQUEST.ALL]",

        "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.ALL]",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xff"

    },

    {
@@ -262,6 +318,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xc2"

    },

    {
@@ -273,6 +330,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x22"

    },

    {
@@ -284,6 +342,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0xc8"

    },

    {
@@ -295,6 +354,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x28"

    },

    {
@@ -305,6 +365,7 @@ 
        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x41"

    },

    {
@@ -424,6 +485,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0xfd"

    },

    {
@@ -970,6 +1032,7 @@ 
        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x80"

    },

    {
@@ -981,6 +1044,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x8"

    },

    {
@@ -992,6 +1056,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -1002,6 +1067,7 @@ 
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x8"

    },

    {
@@ -1013,6 +1079,7 @@ 
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x8"

    },

    {
@@ -1024,6 +1091,7 @@ 
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x4"

    },

    {
@@ -1034,6 +1102,7 @@ 
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x8"

    },

    {
@@ -1045,6 +1114,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -1056,6 +1126,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of PREFETCHW instructions executed.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x8"

    },

    {
@@ -1067,6 +1138,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -1078,6 +1150,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x4"

    }

]

tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json

+6 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
        "EventName": "ARITH.FPDIV_ACTIVE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -19,6 +20,7 @@ 
        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Counts all microcode Floating Point assists.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -29,6 +31,7 @@ 
        "EventName": "ASSISTS.SSE_AVX_MIX",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x10"

    },

    {
@@ -39,6 +42,7 @@ 
        "EventName": "FP_ARITH_DISPATCHED.PORT_0",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -49,6 +53,7 @@ 
        "EventName": "FP_ARITH_DISPATCHED.PORT_1",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -59,6 +64,7 @@ 
        "EventName": "FP_ARITH_DISPATCHED.PORT_5",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x4"

    },

    {

tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json

+16 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",

        "SampleAfterValue": "500009",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -19,6 +20,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -313,6 +315,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.",

        "SampleAfterValue": "500009",

        "Speculative": "1",

        "UMask": "0x4"

    },

    {
@@ -324,6 +327,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",

        "SampleAfterValue": "200003",

        "Speculative": "1",

        "UMask": "0x4"

    },

    {
@@ -336,6 +340,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x8"

    },

    {
@@ -348,6 +353,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x8"

    },

    {
@@ -359,6 +365,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x8"

    },

    {
@@ -371,6 +378,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x4"

    },

    {
@@ -383,6 +391,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x4"

    },

    {
@@ -394,6 +403,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x4"

    },

    {
@@ -406,6 +416,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x20"

    },

    {
@@ -419,6 +430,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x20"

    },

    {
@@ -430,6 +442,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS).",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x20"

    },

    {
@@ -441,6 +454,7 @@ 
        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -453,6 +467,7 @@ 
        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x1"

    },

    {
@@ -466,6 +481,7 @@ 
        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x1"

    }

]

tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json

+11 −1
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x6"

    },

    {
@@ -19,6 +20,7 @@ 
        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -30,6 +32,7 @@ 
        "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -41,6 +44,7 @@ 
        "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x3"

    },

    {
@@ -52,6 +56,7 @@ 
        "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x5"

    },

    {
@@ -63,6 +68,7 @@ 
        "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",

        "PEBScounters": "0,1,2,3",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x9"

    },

    {
@@ -194,12 +200,13 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility.",

        "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",

        "CollectPEBSRecord": "2",

        "Data_LA": "1",

        "EventCode": "0xcd",

        "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",

        "PEBS": "2",

        "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8",

        "SampleAfterValue": "1000003",

        "UMask": "0x2"

    },
@@ -388,6 +395,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x80"

    },

    {
@@ -399,6 +407,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x2"

    },

    {
@@ -410,6 +419,7 @@ 
        "PEBScounters": "0,1,2,3",

        "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x1"

    }

]

tools/perf/pmu-events/arch/x86/sapphirerapids/other.json

+4 −0

File changed.

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