Commit 6a760dc7 authored by Zhang Rui's avatar Zhang Rui Committed by Xiaolong Wang
Browse files

powercap: intel_rapl: Use bitmap for Power Limits 

mainline inclusion
from mainline-v6.5-rc1
commit a38f300b
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I92135

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a38f300bb23c896d2d132a4502086d4bfec2a25e



--------------------------------

Currently, a RAPL package is registered with the number of Power Limits
supported in each RAPL domain. But this doesn't tell which Power Limits
are available. Using the number of Power Limits supported to guess the
availability of each Power Limit is fragile.

Use bitmap to represent the availability of each Power Limit.

Note that PL1 is mandatory thus it does not need to be set explicitly by
the RAPL Interface drivers.

No functional change intended.

Intel-SIG: commit a38f300b powercap: intel_rapl: Use bitmap for Power Limits.    Backport Intel RAPL driver support on TPMI.

Signed-off-by: default avatarZhang Rui <rui.zhang@intel.com>
Tested-by: default avatarWang Wendy <wendy.wang@intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
[ Xiaolong Wang: amend commit log ]
Signed-off-by: default avatarXiaolong Wang <xiaolong.wang@intel.com>
parent 67911bfd

drivers/powercap/intel_rapl_common.c

+6 −8
Original line number Diff line number Diff line
@@ -574,20 +574,18 @@ static void rapl_init_domains(struct rapl_package *rp) 
				rapl_domain_names[i]);



		rd->id = i;



		/* PL1 is supported by default */

		rp->priv->limits[i] |= BIT(POWER_LIMIT1);

		rd->rpl[0].prim_id = PL1_ENABLE;

		rd->rpl[0].name = pl1_name;



		/*

		 * The PL2 power domain is applicable for limits two

		 * and limits three

		 */

		if (rp->priv->limits[i] >= 2) {

		if (rp->priv->limits[i] & BIT(POWER_LIMIT2)) {

			rd->rpl[1].prim_id = PL2_ENABLE;

			rd->rpl[1].name = pl2_name;

		}



		/* Enable PL4 domain if the total power limits are three */

		if (rp->priv->limits[i] == 3) {

		if (rp->priv->limits[i] & BIT(POWER_LIMIT4)) {

			rd->rpl[2].prim_id = PL4_ENABLE;

			rd->rpl[2].name = pl4_name;

		}
@@ -762,7 +760,7 @@ static int rapl_read_data_raw(struct rapl_domain *rd, 
	cpu = rd->rp->lead_cpu;



	/* domain with 2 limits has different bit */

	if (prim == FW_LOCK && rd->rp->priv->limits[rd->id] == 2) {

	if (prim == FW_LOCK && (rd->rp->priv->limits[rd->id] & BIT(POWER_LIMIT2))) {

		rpi->mask = POWER_HIGH_LOCK;

		rpi->shift = 63;

	}

drivers/powercap/intel_rapl_msr.c

+3 −3
Original line number Diff line number Diff line
@@ -44,8 +44,8 @@ static struct rapl_if_priv rapl_msr_priv_intel = { 
		MSR_DRAM_POWER_LIMIT, MSR_DRAM_ENERGY_STATUS, MSR_DRAM_PERF_STATUS, 0, MSR_DRAM_POWER_INFO },

	.regs[RAPL_DOMAIN_PLATFORM] = {

		MSR_PLATFORM_POWER_LIMIT, MSR_PLATFORM_ENERGY_STATUS, 0, 0, 0},

	.limits[RAPL_DOMAIN_PACKAGE] = 2,

	.limits[RAPL_DOMAIN_PLATFORM] = 2,

	.limits[RAPL_DOMAIN_PACKAGE] = BIT(POWER_LIMIT2),

	.limits[RAPL_DOMAIN_PLATFORM] = BIT(POWER_LIMIT2),

};



static struct rapl_if_priv rapl_msr_priv_amd = {
@@ -160,7 +160,7 @@ static int rapl_msr_probe(struct platform_device *pdev) 
	rapl_msr_priv->write_raw = rapl_msr_write_raw;



	if (id) {

		rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] = 3;

		rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |= BIT(POWER_LIMIT4);

		rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4] =

			MSR_VR_CURRENT_CONFIG;

		pr_info("PL4 support detected.\n");

drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

+2 −2
Original line number Diff line number Diff line
@@ -15,8 +15,8 @@ static const struct rapl_mmio_regs rapl_mmio_default = { 
	.reg_unit = 0x5938,

	.regs[RAPL_DOMAIN_PACKAGE] = { 0x59a0, 0x593c, 0x58f0, 0, 0x5930},

	.regs[RAPL_DOMAIN_DRAM] = { 0x58e0, 0x58e8, 0x58ec, 0, 0},

	.limits[RAPL_DOMAIN_PACKAGE] = 2,

	.limits[RAPL_DOMAIN_DRAM] = 2,

	.limits[RAPL_DOMAIN_PACKAGE] = BIT(POWER_LIMIT2),

	.limits[RAPL_DOMAIN_DRAM] = BIT(POWER_LIMIT2),

};



static int rapl_mmio_cpu_online(unsigned int cpu)