Commit 6a6d914d authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Clean up PIPECONF bit defines 



Use REG_BIT() & co. for PIPECONF bits, and adjust the
naming of various bits to be more consistent.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211112193813.8224-5-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 7e31ce58

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -1051,7 +1051,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 


		/* wait for transcoder to be enabled */

		if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),

					  I965_PIPECONF_ACTIVE, 10))

					  PIPECONF_STATE_ENABLE, 10))

			drm_err(&dev_priv->drm,

				"DSI transcoder not enabled\n");

	}
@@ -1319,7 +1319,7 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 


		/* wait for transcoder to be disabled */

		if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),

					    I965_PIPECONF_ACTIVE, 50))

					    PIPECONF_STATE_ENABLE, 50))

			drm_err(&dev_priv->drm,

				"DSI trancoder not disabled\n");

	}

drivers/gpu/drm/i915/display/intel_display.c

+28 −32
Original line number Diff line number Diff line
@@ -391,13 +391,11 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 


	if (DISPLAY_VER(dev_priv) >= 4) {

		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;

		i915_reg_t reg = PIPECONF(cpu_transcoder);



		/* Wait for the Pipe State to go off */

		if (intel_de_wait_for_clear(dev_priv, reg,

					    I965_PIPECONF_ACTIVE, 100))

			drm_WARN(&dev_priv->drm, 1,

				 "pipe_off wait timed out\n");

		if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),

					    PIPECONF_STATE_ENABLE, 100))

			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");

	} else {

		intel_wait_for_pipe_scanline_stopped(crtc);

	}
@@ -3378,13 +3376,13 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 


		switch (crtc_state->pipe_bpp) {

		case 18:

			pipeconf |= PIPECONF_6BPC;

			pipeconf |= PIPECONF_BPC_6;

			break;

		case 24:

			pipeconf |= PIPECONF_8BPC;

			pipeconf |= PIPECONF_BPC_8;

			break;

		case 30:

			pipeconf |= PIPECONF_10BPC;

			pipeconf |= PIPECONF_BPC_10;

			break;

		default:

			/* Case prevented by intel_choose_pipe_bpp_dither. */
@@ -3399,7 +3397,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 
		else

			pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;

	} else {

		pipeconf |= PIPECONF_PROGRESSIVE;

		pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;

	}



	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
@@ -3577,16 +3575,17 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 
	if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||

	    IS_CHERRYVIEW(dev_priv)) {

		switch (tmp & PIPECONF_BPC_MASK) {

		case PIPECONF_6BPC:

		case PIPECONF_BPC_6:

			pipe_config->pipe_bpp = 18;

			break;

		case PIPECONF_8BPC:

		case PIPECONF_BPC_8:

			pipe_config->pipe_bpp = 24;

			break;

		case PIPECONF_10BPC:

		case PIPECONF_BPC_10:

			pipe_config->pipe_bpp = 30;

			break;

		default:

			MISSING_CASE(tmp);

			break;

		}

	}
@@ -3595,8 +3594,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 
	    (tmp & PIPECONF_COLOR_RANGE_SELECT))

		pipe_config->limited_color_range = true;



	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>

		PIPECONF_GAMMA_MODE_SHIFT;

	pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);



	if (IS_CHERRYVIEW(dev_priv))

		pipe_config->cgm_mode = intel_de_read(dev_priv,
@@ -3683,16 +3681,16 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 


	switch (crtc_state->pipe_bpp) {

	case 18:

		val |= PIPECONF_6BPC;

		val |= PIPECONF_BPC_6;

		break;

	case 24:

		val |= PIPECONF_8BPC;

		val |= PIPECONF_BPC_8;

		break;

	case 30:

		val |= PIPECONF_10BPC;

		val |= PIPECONF_BPC_10;

		break;

	case 36:

		val |= PIPECONF_12BPC;

		val |= PIPECONF_BPC_12;

		break;

	default:

		/* Case prevented by intel_choose_pipe_bpp_dither. */
@@ -3700,12 +3698,12 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 
	}



	if (crtc_state->dither)

		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

		val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;



	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

		val |= PIPECONF_INTERLACED_ILK;

		val |= PIPECONF_INTERLACE_IF_ID_ILK;

	else

		val |= PIPECONF_PROGRESSIVE;

		val |= PIPECONF_INTERLACE_PF_PD_ILK;



	/*

	 * This would end up with an odd purple hue over
@@ -3737,12 +3735,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 
	u32 val = 0;



	if (IS_HASWELL(dev_priv) && crtc_state->dither)

		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);

		val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;



	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

		val |= PIPECONF_INTERLACED_ILK;

		val |= PIPECONF_INTERLACE_IF_ID_ILK;

	else

		val |= PIPECONF_PROGRESSIVE;

		val |= PIPECONF_INTERLACE_PF_PD_ILK;



	if (IS_HASWELL(dev_priv) &&

	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
@@ -4036,16 +4034,16 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, 
		goto out;



	switch (tmp & PIPECONF_BPC_MASK) {

	case PIPECONF_6BPC:

	case PIPECONF_BPC_6:

		pipe_config->pipe_bpp = 18;

		break;

	case PIPECONF_8BPC:

	case PIPECONF_BPC_8:

		pipe_config->pipe_bpp = 24;

		break;

	case PIPECONF_10BPC:

	case PIPECONF_BPC_10:

		pipe_config->pipe_bpp = 30;

		break;

	case PIPECONF_12BPC:

	case PIPECONF_BPC_12:

		pipe_config->pipe_bpp = 36;

		break;

	default:
@@ -4065,8 +4063,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, 
		break;

	}



	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>

		PIPECONF_GAMMA_MODE_SHIFT;

	pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);



	pipe_config->csc_mode = intel_de_read(dev_priv,

					      PIPE_CSC_MODE(crtc->pipe));
@@ -10008,8 +10005,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 
		udelay(150); /* wait for warmup */

	}



	intel_de_write(dev_priv, PIPECONF(pipe),

		       PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);

	intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);

	intel_de_posting_read(dev_priv, PIPECONF(pipe));



	intel_wait_for_pipe_scanline_moving(crtc);

drivers/gpu/drm/i915/display/intel_pch_display.c

+3 −4
Original line number Diff line number Diff line
@@ -157,13 +157,13 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) 
		 */

		val &= ~PIPECONF_BPC_MASK;

		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

			val |= PIPECONF_8BPC;

			val |= PIPECONF_BPC_8;

		else

			val |= pipeconf_val & PIPECONF_BPC_MASK;

	}



	val &= ~TRANS_INTERLACE_MASK;

	if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {

	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {

		if (HAS_PCH_IBX(dev_priv) &&

		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))

			val |= TRANS_LEGACY_INTERLACED_ILK;
@@ -436,8 +436,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 
	val = TRANS_ENABLE;

	pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));



	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==

	    PIPECONF_INTERLACED_ILK)

	if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)

		val |= TRANS_INTERLACED;

	else

		val |= TRANS_PROGRESSIVE;

drivers/gpu/drm/i915/gvt/display.c

+2 −2
Original line number Diff line number Diff line
@@ -184,7 +184,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 


		for_each_pipe(dev_priv, pipe) {

			vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=

				~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);

				~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);

			vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;

			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

			vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
@@ -245,7 +245,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
		 *   setup_virtual_dp_monitor.

		 */

		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;

		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;

		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;



		/*

		 * Golden M/N are calculated based on:

drivers/gpu/drm/i915/gvt/handlers.c

+2 −2
Original line number Diff line number Diff line
@@ -702,11 +702,11 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
	data = vgpu_vreg(vgpu, offset);



	if (data & PIPECONF_ENABLE) {

		vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;

		vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE;

		vgpu_update_refresh_rate(vgpu);

		vgpu_update_vblank_emulation(vgpu, true);

	} else {

		vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;

		vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE;

		vgpu_update_vblank_emulation(vgpu, false);

	}

	return 0;