Commit 6a47c304 authored by Lucas Stach's avatar Lucas Stach Committed by Shawn Guo
Browse files

arm64: dts: imx8mq-reform2: add sound support 



This adds sound support to the Reform2.

It differs from the downstream implementation in that the codec
is used as the BCLK and FSYNC master and the i.MX8MQ only supplies
a fixed 25MHz MCLK from the oscillator. This allows to support
a wider range of audio rates by using the codec PLL and to shut
down the audio PLLs on the i.MX8MQ SoC side.

Signed-off-by: default avatarLucas Stach <dev@lynxeye.de>
Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d4efa65f

arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts

+49 −0
Original line number Diff line number Diff line
@@ -40,6 +40,24 @@ 
		regulator-max-microvolt = <5000000>;

		vin-supply = <&reg_main_5v>;

	};



	sound {

		compatible = "fsl,imx-audio-wm8960";

		audio-cpu = <&sai2>;

		audio-codec = <&wm8960>;

		audio-routing =

			"Headphone Jack", "HP_L",

			"Headphone Jack", "HP_R",

			"Ext Spk", "SPK_LP",

			"Ext Spk", "SPK_LN",

			"Ext Spk", "SPK_RP",

			"Ext Spk", "SPK_RN",

			"LINPUT1", "Mic Jack",

			"Mic Jack", "MICB",

			"LINPUT2", "Line In Jack",

			"RINPUT2", "Line In Jack";

		model = "wm8960-audio";

	};

};



&fec1 {
@@ -51,6 +69,14 @@ 
	pinctrl-0 = <&pinctrl_i2c3>;

	status = "okay";



	wm8960: codec@1a {

		compatible = "wlf,wm8960";

		reg = <0x1a>;

		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;

		clock-names = "mclk";

		#sound-dai-cells = <0>;

	};



	rtc@68 {

		compatible = "nxp,pcf8523";

		reg = <0x68>;
@@ -89,6 +115,17 @@ 
	vin-supply = <&reg_main_5v>;

};



&sai2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_sai2>;

	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;

	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;

	assigned-clock-rates = <25000000>;

	fsl,sai-mclk-direction-output;

	fsl,sai-asynchronous;

	status = "okay";

};



&snvs_rtc {

	status = "disabled";

};
@@ -144,6 +181,18 @@ 
		>;

	};



	pinctrl_sai2: sai2grp {

		fsl,pins = <

			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6

			MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6

			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6

			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6

			MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK		0xd6

			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6

			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6

		>;

	};



	pinctrl_uart2: uart2grp {

		fsl,pins = <

			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45