Commit 6a306806 authored by Andrey Grodzovsky's avatar Andrey Grodzovsky Committed by Alex Deucher
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drm/amd: Import smuio_11_0 headers for EEPROM access on Vega20 



v3: Merge CKSVII2C_IC regs into exsisting headers.

Signed-off-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 64f55e62

drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h

+92 −0
Original line number Diff line number Diff line
@@ -29,6 +29,98 @@ 
#define mmSMUSVI0_TEL_PLANE0_BASE_IDX                                                                  0

#define mmSMUIO_MCM_CONFIG                                                                             0x0024

#define mmSMUIO_MCM_CONFIG_BASE_IDX                                                                    0

#define mmCKSVII2C_IC_CON                                                                              0x0040

#define mmCKSVII2C_IC_CON_BASE_IDX                                                                     0

#define mmCKSVII2C_IC_TAR                                                                              0x0041

#define mmCKSVII2C_IC_TAR_BASE_IDX                                                                     0

#define mmCKSVII2C_IC_SAR                                                                              0x0042

#define mmCKSVII2C_IC_SAR_BASE_IDX                                                                     0

#define mmCKSVII2C_IC_HS_MADDR                                                                         0x0043

#define mmCKSVII2C_IC_HS_MADDR_BASE_IDX                                                                0

#define mmCKSVII2C_IC_DATA_CMD                                                                         0x0044

#define mmCKSVII2C_IC_DATA_CMD_BASE_IDX                                                                0

#define mmCKSVII2C_IC_SS_SCL_HCNT                                                                      0x0045

#define mmCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX                                                             0

#define mmCKSVII2C_IC_SS_SCL_LCNT                                                                      0x0046

#define mmCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX                                                             0

#define mmCKSVII2C_IC_FS_SCL_HCNT                                                                      0x0047

#define mmCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX                                                             0

#define mmCKSVII2C_IC_FS_SCL_LCNT                                                                      0x0048

#define mmCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX                                                             0

#define mmCKSVII2C_IC_HS_SCL_HCNT                                                                      0x0049

#define mmCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX                                                             0

#define mmCKSVII2C_IC_HS_SCL_LCNT                                                                      0x004a

#define mmCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX                                                             0

#define mmCKSVII2C_IC_INTR_STAT                                                                        0x004b

#define mmCKSVII2C_IC_INTR_STAT_BASE_IDX                                                               0

#define mmCKSVII2C_IC_INTR_MASK                                                                        0x004c

#define mmCKSVII2C_IC_INTR_MASK_BASE_IDX                                                               0

#define mmCKSVII2C_IC_RAW_INTR_STAT                                                                    0x004d

#define mmCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX                                                           0

#define mmCKSVII2C_IC_RX_TL                                                                            0x004e

#define mmCKSVII2C_IC_RX_TL_BASE_IDX                                                                   0

#define mmCKSVII2C_IC_TX_TL                                                                            0x004f

#define mmCKSVII2C_IC_TX_TL_BASE_IDX                                                                   0

#define mmCKSVII2C_IC_CLR_INTR                                                                         0x0050

#define mmCKSVII2C_IC_CLR_INTR_BASE_IDX                                                                0

#define mmCKSVII2C_IC_CLR_RX_UNDER                                                                     0x0051

#define mmCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX                                                            0

#define mmCKSVII2C_IC_CLR_RX_OVER                                                                      0x0052

#define mmCKSVII2C_IC_CLR_RX_OVER_BASE_IDX                                                             0

#define mmCKSVII2C_IC_CLR_TX_OVER                                                                      0x0053

#define mmCKSVII2C_IC_CLR_TX_OVER_BASE_IDX                                                             0

#define mmCKSVII2C_IC_CLR_RD_REQ                                                                       0x0054

#define mmCKSVII2C_IC_CLR_RD_REQ_BASE_IDX                                                              0

#define mmCKSVII2C_IC_CLR_TX_ABRT                                                                      0x0055

#define mmCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX                                                             0

#define mmCKSVII2C_IC_CLR_RX_DONE                                                                      0x0056

#define mmCKSVII2C_IC_CLR_RX_DONE_BASE_IDX                                                             0

#define mmCKSVII2C_IC_CLR_ACTIVITY                                                                     0x0057

#define mmCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX                                                            0

#define mmCKSVII2C_IC_CLR_STOP_DET                                                                     0x0058

#define mmCKSVII2C_IC_CLR_STOP_DET_BASE_IDX                                                            0

#define mmCKSVII2C_IC_CLR_START_DET                                                                    0x0059

#define mmCKSVII2C_IC_CLR_START_DET_BASE_IDX                                                           0

#define mmCKSVII2C_IC_CLR_GEN_CALL                                                                     0x005a

#define mmCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX                                                            0

#define mmCKSVII2C_IC_ENABLE                                                                           0x005b

#define mmCKSVII2C_IC_ENABLE_BASE_IDX                                                                  0

#define mmCKSVII2C_IC_STATUS                                                                           0x005c

#define mmCKSVII2C_IC_STATUS_BASE_IDX                                                                  0

#define mmCKSVII2C_IC_TXFLR                                                                            0x005d

#define mmCKSVII2C_IC_TXFLR_BASE_IDX                                                                   0

#define mmCKSVII2C_IC_RXFLR                                                                            0x005e

#define mmCKSVII2C_IC_RXFLR_BASE_IDX                                                                   0

#define mmCKSVII2C_IC_SDA_HOLD                                                                         0x005f

#define mmCKSVII2C_IC_SDA_HOLD_BASE_IDX                                                                0

#define mmCKSVII2C_IC_TX_ABRT_SOURCE                                                                   0x0060

#define mmCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX                                                          0

#define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY                                                               0x0061

#define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX                                                      0

#define mmCKSVII2C_IC_DMA_CR                                                                           0x0062

#define mmCKSVII2C_IC_DMA_CR_BASE_IDX                                                                  0

#define mmCKSVII2C_IC_DMA_TDLR                                                                         0x0063

#define mmCKSVII2C_IC_DMA_TDLR_BASE_IDX                                                                0

#define mmCKSVII2C_IC_DMA_RDLR                                                                         0x0064

#define mmCKSVII2C_IC_DMA_RDLR_BASE_IDX                                                                0

#define mmCKSVII2C_IC_SDA_SETUP                                                                        0x0065

#define mmCKSVII2C_IC_SDA_SETUP_BASE_IDX                                                               0

#define mmCKSVII2C_IC_ACK_GENERAL_CALL                                                                 0x0066

#define mmCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX                                                        0

#define mmCKSVII2C_IC_ENABLE_STATUS                                                                    0x0067

#define mmCKSVII2C_IC_ENABLE_STATUS_BASE_IDX                                                           0

#define mmCKSVII2C_IC_FS_SPKLEN                                                                        0x0068

#define mmCKSVII2C_IC_FS_SPKLEN_BASE_IDX                                                               0

#define mmCKSVII2C_IC_HS_SPKLEN                                                                        0x0069

#define mmCKSVII2C_IC_HS_SPKLEN_BASE_IDX                                                               0

#define mmCKSVII2C_IC_CLR_RESTART_DET                                                                  0x006a

#define mmCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX                                                         0

#define mmCKSVII2C_IC_COMP_PARAM_1                                                                     0x006b

#define mmCKSVII2C_IC_COMP_PARAM_1_BASE_IDX                                                            0

#define mmCKSVII2C_IC_COMP_VERSION                                                                     0x006c

#define mmCKSVII2C_IC_COMP_VERSION_BASE_IDX                                                            0

#define mmCKSVII2C_IC_COMP_TYPE                                                                        0x006d

#define mmCKSVII2C_IC_COMP_TYPE_BASE_IDX                                                               0

#define mmSMUIO_MP_RESET_INTR                                                                          0x00c1

#define mmSMUIO_MP_RESET_INTR_BASE_IDX                                                                 0

#define mmSMUIO_SOC_HALT                                                                               0x00c2

drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h

+231 −0

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