Commit 6a1dc68e authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'lan966x-qos' 



Horatiu Vultur says:

====================
net: lan966x: Add tbf, cbs, ets support

Add support for offloading QoS features with tc command to lan966x.
The offloaded Qos features are tbf, cbs and ets.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 2ae3cb58 29aaf3d4

drivers/net/ethernet/microchip/lan966x/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -9,4 +9,5 @@ lan966x-switch-objs := lan966x_main.o lan966x_phylink.o lan966x_port.o \ 
			lan966x_mac.o lan966x_ethtool.o lan966x_switchdev.o \

			lan966x_vlan.o lan966x_fdb.o lan966x_mdb.o \

			lan966x_ptp.o lan966x_fdma.o lan966x_lag.o \

			lan966x_tc.o lan966x_mqprio.o lan966x_taprio.o
 
			lan966x_tc.o lan966x_mqprio.o lan966x_taprio.o \

			lan966x_tbf.o lan966x_cbs.o lan966x_ets.o

drivers/net/ethernet/microchip/lan966x/lan966x_cbs.c

0 → 100644
+70 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+



#include "lan966x_main.h"



int lan966x_cbs_add(struct lan966x_port *port,

		    struct tc_cbs_qopt_offload *qopt)

{

	struct lan966x *lan966x = port->lan966x;

	u32 cir, cbs;

	u8 se_idx;



	/* Check for invalid values */

	if (qopt->idleslope <= 0 ||

	    qopt->sendslope >= 0 ||

	    qopt->locredit >= qopt->hicredit)

		return -EINVAL;



	se_idx = SE_IDX_QUEUE + port->chip_port * NUM_PRIO_QUEUES + qopt->queue;

	cir = qopt->idleslope;

	cbs = (qopt->idleslope - qopt->sendslope) *

		(qopt->hicredit - qopt->locredit) /

		-qopt->sendslope;



	/* Rate unit is 100 kbps */

	cir = DIV_ROUND_UP(cir, 100);

	/* Avoid using zero rate */

	cir = cir ?: 1;

	/* Burst unit is 4kB */

	cbs = DIV_ROUND_UP(cbs, 4096);

	/* Avoid using zero burst */

	cbs = cbs ?: 1;



	/* Check that actually the result can be written */

	if (cir > GENMASK(15, 0) ||

	    cbs > GENMASK(6, 0))

		return -EINVAL;



	lan_rmw(QSYS_SE_CFG_SE_AVB_ENA_SET(1) |

		QSYS_SE_CFG_SE_FRM_MODE_SET(1),

		QSYS_SE_CFG_SE_AVB_ENA |

		QSYS_SE_CFG_SE_FRM_MODE,

		lan966x, QSYS_SE_CFG(se_idx));



	lan_wr(QSYS_CIR_CFG_CIR_RATE_SET(cir) |

	       QSYS_CIR_CFG_CIR_BURST_SET(cbs),

	       lan966x, QSYS_CIR_CFG(se_idx));



	return 0;

}



int lan966x_cbs_del(struct lan966x_port *port,

		    struct tc_cbs_qopt_offload *qopt)

{

	struct lan966x *lan966x = port->lan966x;

	u8 se_idx;



	se_idx = SE_IDX_QUEUE + port->chip_port * NUM_PRIO_QUEUES + qopt->queue;



	lan_rmw(QSYS_SE_CFG_SE_AVB_ENA_SET(1) |

		QSYS_SE_CFG_SE_FRM_MODE_SET(0),

		QSYS_SE_CFG_SE_AVB_ENA |

		QSYS_SE_CFG_SE_FRM_MODE,

		lan966x, QSYS_SE_CFG(se_idx));



	lan_wr(QSYS_CIR_CFG_CIR_RATE_SET(0) |

	       QSYS_CIR_CFG_CIR_BURST_SET(0),

	       lan966x, QSYS_CIR_CFG(se_idx));



	return 0;

}

drivers/net/ethernet/microchip/lan966x/lan966x_ets.c

0 → 100644
+96 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+



#include "lan966x_main.h"



#define DWRR_COST_BIT_WIDTH	BIT(5)



static u32 lan966x_ets_hw_cost(u32 w_min, u32 weight)

{

	u32 res;



	/* Round half up: Multiply with 16 before division,

	 * add 8 and divide result with 16 again

	 */

	res = (((DWRR_COST_BIT_WIDTH << 4) * w_min / weight) + 8) >> 4;

	return max_t(u32, 1, res) - 1;

}



int lan966x_ets_add(struct lan966x_port *port,

		    struct tc_ets_qopt_offload *qopt)

{

	struct tc_ets_qopt_offload_replace_params *params;

	struct lan966x *lan966x = port->lan966x;

	u32 w_min = 100;

	u8 count = 0;

	u32 se_idx;

	u8 i;



	/* Check the input */

	if (qopt->parent != TC_H_ROOT)

		return -EINVAL;



	params = &qopt->replace_params;

	if (params->bands != NUM_PRIO_QUEUES)

		return -EINVAL;



	for (i = 0; i < params->bands; ++i) {

		/* In the switch the DWRR is always on the lowest consecutive

		 * priorities. Due to this, the first priority must map to the

		 * first DWRR band.

		 */

		if (params->priomap[i] != (7 - i))

			return -EINVAL;



		if (params->quanta[i] && params->weights[i] == 0)

			return -EINVAL;

	}



	se_idx = SE_IDX_PORT + port->chip_port;



	/* Find minimum weight */

	for (i = 0; i < params->bands; ++i) {

		if (params->quanta[i] == 0)

			continue;



		w_min = min(w_min, params->weights[i]);

	}



	for (i = 0; i < params->bands; ++i) {

		if (params->quanta[i] == 0)

			continue;



		++count;



		lan_wr(lan966x_ets_hw_cost(w_min, params->weights[i]),

		       lan966x, QSYS_SE_DWRR_CFG(se_idx, 7 - i));

	}



	lan_rmw(QSYS_SE_CFG_SE_DWRR_CNT_SET(count) |

		QSYS_SE_CFG_SE_RR_ENA_SET(0),

		QSYS_SE_CFG_SE_DWRR_CNT |

		QSYS_SE_CFG_SE_RR_ENA,

		lan966x, QSYS_SE_CFG(se_idx));



	return 0;

}



int lan966x_ets_del(struct lan966x_port *port,

		    struct tc_ets_qopt_offload *qopt)

{

	struct lan966x *lan966x = port->lan966x;

	u32 se_idx;

	int i;



	se_idx = SE_IDX_PORT + port->chip_port;



	for (i = 0; i < NUM_PRIO_QUEUES; ++i)

		lan_wr(0, lan966x, QSYS_SE_DWRR_CFG(se_idx, i));



	lan_rmw(QSYS_SE_CFG_SE_DWRR_CNT_SET(0) |

		QSYS_SE_CFG_SE_RR_ENA_SET(0),

		QSYS_SE_CFG_SE_DWRR_CNT |

		QSYS_SE_CFG_SE_RR_ENA,

		lan966x, QSYS_SE_CFG(se_idx));



	return 0;

}

drivers/net/ethernet/microchip/lan966x/lan966x_main.h

+19 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/phy.h>

#include <linux/phylink.h>

#include <linux/ptp_clock_kernel.h>

#include <net/pkt_cls.h>

#include <net/pkt_sched.h>

#include <net/switchdev.h>
@@ -81,6 +82,9 @@ 
#define FDMA_INJ_CHANNEL		0

#define FDMA_DCB_MAX			512



#define SE_IDX_QUEUE			0  /* 0-79 : Queue scheduler elements */

#define SE_IDX_PORT			80 /* 80-89 : Port schedular elements */



/* MAC table entry types.

 * ENTRYTYPE_NORMAL is subject to aging.

 * ENTRYTYPE_LOCKED is not subject to aging.
@@ -462,6 +466,21 @@ int lan966x_taprio_add(struct lan966x_port *port, 
int lan966x_taprio_del(struct lan966x_port *port);

int lan966x_taprio_speed_set(struct lan966x_port *port, int speed);



int lan966x_tbf_add(struct lan966x_port *port,

		    struct tc_tbf_qopt_offload *qopt);

int lan966x_tbf_del(struct lan966x_port *port,

		    struct tc_tbf_qopt_offload *qopt);



int lan966x_cbs_add(struct lan966x_port *port,

		    struct tc_cbs_qopt_offload *qopt);

int lan966x_cbs_del(struct lan966x_port *port,

		    struct tc_cbs_qopt_offload *qopt);



int lan966x_ets_add(struct lan966x_port *port,

		    struct tc_ets_qopt_offload *qopt);

int lan966x_ets_del(struct lan966x_port *port,

		    struct tc_ets_qopt_offload *qopt);



static inline void __iomem *lan_addr(void __iomem *base[],

				     int id, int tinst, int tcnt,

				     int gbase, int ginst,

drivers/net/ethernet/microchip/lan966x/lan966x_regs.h

+50 −0
Original line number Diff line number Diff line
@@ -1018,6 +1018,56 @@ enum lan966x_target { 
/*      QSYS:RES_CTRL:RES_CFG */

#define QSYS_RES_CFG(g)           __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4)



/*      QSYS:HSCH:CIR_CFG */

#define QSYS_CIR_CFG(g)           __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 0, 0, 1, 4)



#define QSYS_CIR_CFG_CIR_RATE                    GENMASK(20, 6)

#define QSYS_CIR_CFG_CIR_RATE_SET(x)\

	FIELD_PREP(QSYS_CIR_CFG_CIR_RATE, x)

#define QSYS_CIR_CFG_CIR_RATE_GET(x)\

	FIELD_GET(QSYS_CIR_CFG_CIR_RATE, x)



#define QSYS_CIR_CFG_CIR_BURST                   GENMASK(5, 0)

#define QSYS_CIR_CFG_CIR_BURST_SET(x)\

	FIELD_PREP(QSYS_CIR_CFG_CIR_BURST, x)

#define QSYS_CIR_CFG_CIR_BURST_GET(x)\

	FIELD_GET(QSYS_CIR_CFG_CIR_BURST, x)



/*      QSYS:HSCH:SE_CFG */

#define QSYS_SE_CFG(g)            __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4)



#define QSYS_SE_CFG_SE_DWRR_CNT                  GENMASK(9, 6)

#define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\

	FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x)

#define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\

	FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x)



#define QSYS_SE_CFG_SE_RR_ENA                    BIT(5)

#define QSYS_SE_CFG_SE_RR_ENA_SET(x)\

	FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x)

#define QSYS_SE_CFG_SE_RR_ENA_GET(x)\

	FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x)



#define QSYS_SE_CFG_SE_AVB_ENA                   BIT(4)

#define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\

	FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x)

#define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\

	FIELD_GET(QSYS_SE_CFG_SE_AVB_ENA, x)



#define QSYS_SE_CFG_SE_FRM_MODE                  GENMASK(3, 2)

#define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\

	FIELD_PREP(QSYS_SE_CFG_SE_FRM_MODE, x)

#define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\

	FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x)



#define QSYS_SE_DWRR_CFG(g, r)    __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4)



#define QSYS_SE_DWRR_CFG_DWRR_COST               GENMASK(4, 0)

#define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\

	FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x)

#define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\

	FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x)



/*      QSYS:TAS_CONFIG:TAS_CFG_CTRL */

#define QSYS_TAS_CFG_CTRL         __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4)