Commit 6a0fe0be authored by Liao Xuan's avatar Liao Xuan
Browse files

EDAC/amd64: Add support for Hygon family 18h model 10h 

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9VW9Q


CVE: NA

---------------------------

Add Hygon family 18h model 10h processor support for amd64_edac.

Signed-off-by: default avatarLiao Xuan <liaoxuan@hygon.cn>
parent ba0b64b1

drivers/edac/amd64_edac.c

+14 −0
Original line number Diff line number Diff line
@@ -2443,6 +2443,16 @@ static struct amd64_family_type family_types[] = { 
			.dbam_to_cs		= f17_addr_mask_to_cs_size,

		}

	},

	[F18_M10H_CPUS] = {

		.ctl_name = "F18h_M10h",

		.f0_id = PCI_DEVICE_ID_HYGON_18H_M10H_DF_F0,

		.f6_id = PCI_DEVICE_ID_HYGON_18H_M10H_DF_F6,

		.max_mcs = 2,

		.ops = {

			.early_channel_count	= f17_early_channel_count,

			.dbam_to_cs		= f17_addr_mask_to_cs_size,

		}

	},

	[F19_CPUS] = {

		.ctl_name = "F19h",

		.f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0,
@@ -3558,6 +3568,10 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) 
			fam_type = &family_types[F18_M06H_CPUS];

			pvt->ops = &family_types[F18_M06H_CPUS].ops;

			break;

		} else if (pvt->model == 0x10) {

			fam_type = &family_types[F18_M10H_CPUS];

			pvt->ops = &family_types[F18_M10H_CPUS].ops;

			break;

		}

		fam_type	= &family_types[F17_CPUS];

		pvt->ops	= &family_types[F17_CPUS].ops;

drivers/edac/amd64_edac.h

+3 −0
Original line number Diff line number Diff line
@@ -129,6 +129,8 @@ 


#define PCI_DEVICE_ID_HYGON_18H_M06H_DF_F0 0x14b0

#define PCI_DEVICE_ID_HYGON_18H_M06H_DF_F6 0x14b6

#define PCI_DEVICE_ID_HYGON_18H_M10H_DF_F0 0x14d0

#define PCI_DEVICE_ID_HYGON_18H_M10H_DF_F6 0x14d6



/*

 * Function 1 - Address Map
@@ -303,6 +305,7 @@ enum amd_families { 
	F17_M30H_CPUS,

	F17_M70H_CPUS,

	F18_M06H_CPUS,

	F18_M10H_CPUS,

	F19_CPUS,

	F19_M10H_CPUS,

	NUM_FAMILIES,