Commit 69f8afdb authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/pvc: Engine definitions for new copy engines 



This patch adds the basic definitions needed to support
new copy engines. Also updating the cmd_info to accommodate
new engines, as the engine id's of legacy engines have been
changed.

v2:
 - Add _BCS(n) definition, similar to other engines.  (Tvrtko)
 - Add I915_MAX_BCS definition, similar to other engnes.  (Prathap)
 - Move GVT change to avoid u16 overflow to its own patch.  (Tvrtko)

Original-author: CQ Tang
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-9-matthew.d.roper@intel.com
parent 93d9e045

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+56 −0
Original line number Diff line number Diff line
@@ -71,6 +71,62 @@ static const struct engine_info intel_engines[] = { 
			{ .graphics_ver = 6, .base = BLT_RING_BASE }

		},

	},

	[BCS1] = {

		.class = COPY_ENGINE_CLASS,

		.instance = 1,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }

		},

	},

	[BCS2] = {

		.class = COPY_ENGINE_CLASS,

		.instance = 2,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }

		},

	},

	[BCS3] = {

		.class = COPY_ENGINE_CLASS,

		.instance = 3,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }

		},

	},

	[BCS4] = {

		.class = COPY_ENGINE_CLASS,

		.instance = 4,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }

		},

	},

	[BCS5] = {

		.class = COPY_ENGINE_CLASS,

		.instance = 5,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }

		},

	},

	[BCS6] = {

		.class = COPY_ENGINE_CLASS,

		.instance = 6,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }

		},

	},

	[BCS7] = {

		.class = COPY_ENGINE_CLASS,

		.instance = 7,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }

		},

	},

	[BCS8] = {

		.class = COPY_ENGINE_CLASS,

		.instance = 8,

		.mmio_bases = {

			{ .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }

		},

	},

	[VCS0] = {

		.class = VIDEO_DECODE_CLASS,

		.instance = 0,

drivers/gpu/drm/i915/gt/intel_engine_types.h

+11 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ 
#define OTHER_CLASS		4

#define COMPUTE_CLASS		5

#define MAX_ENGINE_CLASS	5

#define MAX_ENGINE_INSTANCE	7

#define MAX_ENGINE_INSTANCE	8



#define I915_MAX_SLICES	3

#define I915_MAX_SUBSLICES 8
@@ -99,6 +99,7 @@ struct i915_ctx_workarounds { 
#define I915_MAX_SFC	(I915_MAX_VCS / 2)

#define I915_MAX_CCS	4

#define I915_MAX_RCS	1

#define I915_MAX_BCS	9



/*

 * Engine IDs definitions.
@@ -107,6 +108,15 @@ struct i915_ctx_workarounds { 
enum intel_engine_id {

	RCS0 = 0,

	BCS0,

	BCS1,

	BCS2,

	BCS3,

	BCS4,

	BCS5,

	BCS6,

	BCS7,

	BCS8,

#define _BCS(n) (BCS0 + (n))

	VCS0,

	VCS1,

	VCS2,

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+8 −0
Original line number Diff line number Diff line
@@ -1476,6 +1476,14 @@ 
#define   GEN11_KCR				(19)

#define   GEN11_GTPM				(16)

#define   GEN11_BCS				(15)

#define   XEHPC_BCS1				(14)

#define   XEHPC_BCS2				(13)

#define   XEHPC_BCS3				(12)

#define   XEHPC_BCS4				(11)

#define   XEHPC_BCS5				(10)

#define   XEHPC_BCS6				(9)

#define   XEHPC_BCS7				(8)

#define   XEHPC_BCS8				(23)

#define   GEN12_CCS3				(7)

#define   GEN12_CCS2				(6)

#define   GEN12_CCS1				(5)

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -976,6 +976,14 @@ 
#define GEN12_COMPUTE2_RING_BASE	0x1e000

#define GEN12_COMPUTE3_RING_BASE	0x26000

#define BLT_RING_BASE		0x22000

#define XEHPC_BCS1_RING_BASE	0x3e0000

#define XEHPC_BCS2_RING_BASE	0x3e2000

#define XEHPC_BCS3_RING_BASE	0x3e4000

#define XEHPC_BCS4_RING_BASE	0x3e6000

#define XEHPC_BCS5_RING_BASE	0x3e8000

#define XEHPC_BCS6_RING_BASE	0x3ea000

#define XEHPC_BCS7_RING_BASE	0x3ec000

#define XEHPC_BCS8_RING_BASE	0x3ee000

#define DG1_GSC_HECI1_BASE	0x00258000

#define DG1_GSC_HECI2_BASE	0x00259000

#define DG2_GSC_HECI1_BASE	0x00373000