Commit 69e5fe4a authored by Yi Liu's avatar Yi Liu Committed by Jason Zeng
Browse files

iommu/vt-d: Add __iommu_flush_iotlb_psi() 

mainline inclusion
from mainline-v6.8-rc6
commit 0455d317f533e4427ddaa805563ff48711f05810
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I938E2
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0455d317f533e4427ddaa805563ff48711f05810



--------------------------------

Add __iommu_flush_iotlb_psi() to do the psi iotlb flush with a DID input
rather than calculating it within the helper.

This is useful when flushing cache for parent domain which reuses DIDs of
its nested domains.

Signed-off-by: default avatarYi Liu <yi.l.liu@intel.com>
Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20240208082307.15759-3-yi.l.liu@intel.com


Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
Signed-off-by: default avatarJason Zeng <jason.zeng@intel.com>
parent ed44d9df

drivers/iommu/intel/iommu.c

+43 −35
Original line number Diff line number Diff line
@@ -1367,26 +1367,14 @@ static void domain_flush_pasid_iotlb(struct intel_iommu *iommu, 
	spin_unlock_irqrestore(&domain->lock, flags);

}



static void iommu_flush_iotlb_psi(struct intel_iommu *iommu,

				  struct dmar_domain *domain,

static void __iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,

				    unsigned long pfn, unsigned int pages,

				  int ih, int map)

				    int ih)

{

	unsigned int aligned_pages = __roundup_pow_of_two(pages);

	unsigned int mask = ilog2(aligned_pages);

	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;

	u16 did = domain_id_iommu(domain, iommu);



	if (WARN_ON(!pages))

		return;



	if (ih)

		ih = 1 << 6;



	if (domain->use_first_level) {

		domain_flush_pasid_iotlb(iommu, domain, addr, pages, ih);

	} else {

	unsigned long bitmask = aligned_pages - 1;

	unsigned int mask = ilog2(aligned_pages);

	u64 addr = (u64)pfn << VTD_PAGE_SHIFT;



	/*

	 * PSI masks the low order bits of the base address. If the
@@ -1411,8 +1399,7 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, 
	 * Fallback to domain selective flush if no PSI support or

	 * the size is too big.

	 */

		if (!cap_pgsel_inv(iommu->cap) ||

		    mask > cap_max_amask_val(iommu->cap))

	if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))

		iommu->flush.flush_iotlb(iommu, did, 0, 0,

					 DMA_TLB_DSI_FLUSH);

	else
@@ -1420,6 +1407,27 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, 
					 DMA_TLB_PSI_FLUSH);

}



static void iommu_flush_iotlb_psi(struct intel_iommu *iommu,

				  struct dmar_domain *domain,

				  unsigned long pfn, unsigned int pages,

				  int ih, int map)

{

	unsigned int aligned_pages = __roundup_pow_of_two(pages);

	unsigned int mask = ilog2(aligned_pages);

	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;

	u16 did = domain_id_iommu(domain, iommu);



	if (WARN_ON(!pages))

		return;



	if (ih)

		ih = 1 << 6;



	if (domain->use_first_level)

		domain_flush_pasid_iotlb(iommu, domain, addr, pages, ih);

	else

		__iommu_flush_iotlb_psi(iommu, did, pfn, pages, ih);



	/*

	 * In caching mode, changes of pages from non-present to present require

	 * flush. However, device IOTLB doesn't need to be flushed in this case.