Commit 69b93104 authored by Yixun Lan's avatar Yixun Lan Committed by Jerome Brunet
Browse files

clk: meson-axg: pcie: drop the mpll3 clock parent 



We found the PCIe driver doesn't really work with
the mpll3 clock which is actually reserved for debug,
So drop it from the mux list.

Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
Tested-by: default avatarJianxin Qin <jianxin.qin@amlogic.com>
Signed-off-by: default avatarYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 56dbabc0

drivers/clk/meson/axg.c

+4 −2
Original line number Diff line number Diff line
@@ -730,12 +730,14 @@ static struct clk_regmap axg_pcie_mux = { 
		.offset = HHI_PCIE_PLL_CNTL6,

		.mask = 0x1,

		.shift = 2,

		/* skip the parent mpll3, reserved for debug */

		.table = (u32[]){ 1 },

	},

	.hw.init = &(struct clk_init_data){

		.name = "pcie_mux",

		.ops = &clk_regmap_mux_ops,

		.parent_names = (const char *[]){ "mpll3", "pcie_pll" },

		.num_parents = 2,

		.parent_names = (const char *[]){ "pcie_pll" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};