Commit 699aa57b authored by Zhenyu Wang's avatar Zhenyu Wang
Browse files

drm/i915/gvt: Fix cached atomics setting for Windows VM 



We've seen recent regression with host and windows VM running
simultaneously that cause gpu hang or even crash. Finally bisect to
commit 58586680 ("drm/i915: Disable atomics in L3 for gen9"),
which seems cached atomics behavior difference caused regression
issue.

This tries to add new scratch register handler and add those in mmio
save/restore list for context switch. No gpu hang produced with this one.

Cc: stable@vger.kernel.org # 5.12+
Cc: "Xu, Terrence" <terrence.xu@intel.com>
Cc: "Bloomfield, Jon" <jon.bloomfield@intel.com>
Cc: "Ekstrand, Jason" <jason.ekstrand@intel.com>
Reviewed-by: default avatarColin Xu <colin.xu@intel.com>
Fixes: 58586680 ("drm/i915: Disable atomics in L3 for gen9")
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210806044056.648016-1-zhenyuw@linux.intel.com
parent c90b4503

drivers/gpu/drm/i915/gvt/handlers.c

+1 −0
Original line number Diff line number Diff line
@@ -3149,6 +3149,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt) 
	MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);

	MMIO_D(_MMIO(0xb110), D_BDW);

	MMIO_D(GEN9_SCRATCH_LNCF1, D_BDW_PLUS);



	MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,

		D_BDW_PLUS, NULL, force_nonpriv_write);

drivers/gpu/drm/i915/gvt/mmio_context.c

+2 −0
Original line number Diff line number Diff line
@@ -105,6 +105,8 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 
	{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */

	{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */

	{RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */

	{RCS0, GEN9_SCRATCH1, 0, false}, /* 0xb11c */

	{RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */

	{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */

	{RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */

	{RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */