Loading arch/arm/mach-s3c2410/clock.c +1 −1 Original line number Diff line number Diff line Loading @@ -478,7 +478,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev) { unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate) * 2; s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate); printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n", print_mhz(s3c2440_clk_upll.rate)); Loading arch/arm/mach-s3c2410/s3c2440.c +4 −2 Original line number Diff line number Diff line Loading @@ -192,9 +192,11 @@ void __init s3c2440_map_io(struct map_desc *mach_desc, int size) iotable_init(s3c2440_iodesc, ARRAY_SIZE(s3c2440_iodesc)); iotable_init(mach_desc, size); /* rename any peripherals used differing from the s3c2410 */ s3c_device_i2c.name = "s3c2440-i2c"; s3c_device_nand.name = "s3c2440-nand"; /* change irq for watchdog */ Loading Loading @@ -225,7 +227,7 @@ void __init s3c2440_init_clocks(int xtal) break; case S3C2440_CLKDIVN_HDIVN_2: hdiv = 1; hdiv = 2; break; case S3C2440_CLKDIVN_HDIVN_4_8: Loading arch/arm/mm/Kconfig +10 −11 Original line number Diff line number Diff line Loading @@ -412,21 +412,20 @@ config CPU_BPREDICT_DISABLE config TLS_REG_EMUL bool default y if (SMP || CPU_32v6) && (CPU_32v5 || CPU_32v4 || CPU_32v3) default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3) help We might be running on an ARMv6+ processor which should have the TLS register but for some reason we can't use it, or maybe an SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to that register must be emulated. An SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to that required register must be emulated. config HAS_TLS_REG bool depends on CPU_32v6 default y if !TLS_REG_EMUL depends on !TLS_REG_EMUL default y if SMP || CPU_32v7 help This selects support for the CP15 thread register. It is defined to be available on ARMv6 or later. If a particular ARMv6 or later CPU doesn't support it then it must omc;ide "select TLS_REG_EMUL" along with its other caracteristics. It is defined to be available on some ARMv6 processors (including all SMP capable ARMv6's) or later processors. User space may assume directly accessing that register and always obtain the expected value only on ARMv7 and above. arch/arm/mm/copypage-v4mc.Sdeleted 100644 → 0 +0 −80 Original line number Diff line number Diff line /* * linux/arch/arm/lib/copy_page-armv4mc.S * * Copyright (C) 1995-2001 Russell King * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * ASM optimised string functions */ #include <linux/linkage.h> #include <linux/init.h> #include <asm/constants.h> .text .align 5 /* * ARMv4 mini-dcache optimised copy_user_page * * We flush the destination cache lines just before we write the data into the * corresponding address. Since the Dcache is read-allocate, this removes the * Dcache aliasing issue. The writes will be forwarded to the write buffer, * and merged as appropriate. * * Note: We rely on all ARMv4 processors implementing the "invalidate D line" * instruction. If your processor does not supply this, you have to write your * own copy_user_page that does the right thing. */ ENTRY(v4_mc_copy_user_page) stmfd sp!, {r4, lr} @ 2 mov r4, r0 mov r0, r1 bl map_page_minicache mov r1, #PAGE_SZ/64 @ 1 ldmia r0!, {r2, r3, ip, lr} @ 4 1: mcr p15, 0, r4, c7, c6, 1 @ 1 invalidate D line stmia r4!, {r2, r3, ip, lr} @ 4 ldmia r0!, {r2, r3, ip, lr} @ 4+1 stmia r4!, {r2, r3, ip, lr} @ 4 ldmia r0!, {r2, r3, ip, lr} @ 4 mcr p15, 0, r4, c7, c6, 1 @ 1 invalidate D line stmia r4!, {r2, r3, ip, lr} @ 4 ldmia r0!, {r2, r3, ip, lr} @ 4 subs r1, r1, #1 @ 1 stmia r4!, {r2, r3, ip, lr} @ 4 ldmneia r0!, {r2, r3, ip, lr} @ 4 bne 1b @ 1 ldmfd sp!, {r4, pc} @ 3 .align 5 /* * ARMv4 optimised clear_user_page * * Same story as above. */ ENTRY(v4_mc_clear_user_page) str lr, [sp, #-4]! mov r1, #PAGE_SZ/64 @ 1 mov r2, #0 @ 1 mov r3, #0 @ 1 mov ip, #0 @ 1 mov lr, #0 @ 1 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line stmia r0!, {r2, r3, ip, lr} @ 4 stmia r0!, {r2, r3, ip, lr} @ 4 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line stmia r0!, {r2, r3, ip, lr} @ 4 stmia r0!, {r2, r3, ip, lr} @ 4 subs r1, r1, #1 @ 1 bne 1b @ 1 ldr pc, [sp], #4 __INITDATA .type v4_mc_user_fns, #object ENTRY(v4_mc_user_fns) .long v4_mc_clear_user_page .long v4_mc_copy_user_page .size v4_mc_user_fns, . - v4_mc_user_fns arch/arm/mm/copypage-v4mc.c 0 → 100644 +111 −0 Original line number Diff line number Diff line /* * linux/arch/arm/lib/copypage-armv4mc.S * * Copyright (C) 1995-2005 Russell King * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This handles the mini data cache, as found on SA11x0 and XScale * processors. When we copy a user page page, we map it in such a way * that accesses to this page will not touch the main data cache, but * will be cached in the mini data cache. This prevents us thrashing * the main data cache on page faults. */ #include <linux/init.h> #include <linux/mm.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> /* * 0xffff8000 to 0xffffffff is reserved for any ARM architecture * specific hacks for copying pages efficiently. */ #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ L_PTE_CACHEABLE) #define TOP_PTE(x) pte_offset_kernel(top_pmd, x) static DEFINE_SPINLOCK(minicache_lock); /* * ARMv4 mini-dcache optimised copy_user_page * * We flush the destination cache lines just before we write the data into the * corresponding address. Since the Dcache is read-allocate, this removes the * Dcache aliasing issue. The writes will be forwarded to the write buffer, * and merged as appropriate. * * Note: We rely on all ARMv4 processors implementing the "invalidate D line" * instruction. If your processor does not supply this, you have to write your * own copy_user_page that does the right thing. */ static void __attribute__((naked)) mc_copy_user_page(void *from, void *to) { asm volatile( "stmfd sp!, {r4, lr} @ 2\n\ mov r4, %2 @ 1\n\ ldmia %0!, {r2, r3, ip, lr} @ 4\n\ 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ stmia %1!, {r2, r3, ip, lr} @ 4\n\ ldmia %0!, {r2, r3, ip, lr} @ 4+1\n\ stmia %1!, {r2, r3, ip, lr} @ 4\n\ ldmia %0!, {r2, r3, ip, lr} @ 4\n\ mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ stmia %1!, {r2, r3, ip, lr} @ 4\n\ ldmia %0!, {r2, r3, ip, lr} @ 4\n\ subs r4, r4, #1 @ 1\n\ stmia %1!, {r2, r3, ip, lr} @ 4\n\ ldmneia %0!, {r2, r3, ip, lr} @ 4\n\ bne 1b @ 1\n\ ldmfd sp!, {r4, pc} @ 3" : : "r" (from), "r" (to), "I" (PAGE_SIZE / 64)); } void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) { spin_lock(&minicache_lock); set_pte(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot)); flush_tlb_kernel_page(0xffff8000); mc_copy_user_page((void *)0xffff8000, kto); spin_unlock(&minicache_lock); } /* * ARMv4 optimised clear_user_page */ void __attribute__((naked)) v4_mc_clear_user_page(void *kaddr, unsigned long vaddr) { asm volatile( "str lr, [sp, #-4]!\n\ mov r1, %0 @ 1\n\ mov r2, #0 @ 1\n\ mov r3, #0 @ 1\n\ mov ip, #0 @ 1\n\ mov lr, #0 @ 1\n\ 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ stmia r0!, {r2, r3, ip, lr} @ 4\n\ stmia r0!, {r2, r3, ip, lr} @ 4\n\ mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ stmia r0!, {r2, r3, ip, lr} @ 4\n\ stmia r0!, {r2, r3, ip, lr} @ 4\n\ subs r1, r1, #1 @ 1\n\ bne 1b @ 1\n\ ldr pc, [sp], #4" : : "I" (PAGE_SIZE / 64)); } struct cpu_user_fns v4_mc_user_fns __initdata = { .cpu_clear_user_page = v4_mc_clear_user_page, .cpu_copy_user_page = v4_mc_copy_user_page, }; Loading
arch/arm/mach-s3c2410/clock.c +1 −1 Original line number Diff line number Diff line Loading @@ -478,7 +478,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev) { unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate) * 2; s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal.rate); printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n", print_mhz(s3c2440_clk_upll.rate)); Loading
arch/arm/mach-s3c2410/s3c2440.c +4 −2 Original line number Diff line number Diff line Loading @@ -192,9 +192,11 @@ void __init s3c2440_map_io(struct map_desc *mach_desc, int size) iotable_init(s3c2440_iodesc, ARRAY_SIZE(s3c2440_iodesc)); iotable_init(mach_desc, size); /* rename any peripherals used differing from the s3c2410 */ s3c_device_i2c.name = "s3c2440-i2c"; s3c_device_nand.name = "s3c2440-nand"; /* change irq for watchdog */ Loading Loading @@ -225,7 +227,7 @@ void __init s3c2440_init_clocks(int xtal) break; case S3C2440_CLKDIVN_HDIVN_2: hdiv = 1; hdiv = 2; break; case S3C2440_CLKDIVN_HDIVN_4_8: Loading
arch/arm/mm/Kconfig +10 −11 Original line number Diff line number Diff line Loading @@ -412,21 +412,20 @@ config CPU_BPREDICT_DISABLE config TLS_REG_EMUL bool default y if (SMP || CPU_32v6) && (CPU_32v5 || CPU_32v4 || CPU_32v3) default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3) help We might be running on an ARMv6+ processor which should have the TLS register but for some reason we can't use it, or maybe an SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to that register must be emulated. An SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to that required register must be emulated. config HAS_TLS_REG bool depends on CPU_32v6 default y if !TLS_REG_EMUL depends on !TLS_REG_EMUL default y if SMP || CPU_32v7 help This selects support for the CP15 thread register. It is defined to be available on ARMv6 or later. If a particular ARMv6 or later CPU doesn't support it then it must omc;ide "select TLS_REG_EMUL" along with its other caracteristics. It is defined to be available on some ARMv6 processors (including all SMP capable ARMv6's) or later processors. User space may assume directly accessing that register and always obtain the expected value only on ARMv7 and above.
arch/arm/mm/copypage-v4mc.Sdeleted 100644 → 0 +0 −80 Original line number Diff line number Diff line /* * linux/arch/arm/lib/copy_page-armv4mc.S * * Copyright (C) 1995-2001 Russell King * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * ASM optimised string functions */ #include <linux/linkage.h> #include <linux/init.h> #include <asm/constants.h> .text .align 5 /* * ARMv4 mini-dcache optimised copy_user_page * * We flush the destination cache lines just before we write the data into the * corresponding address. Since the Dcache is read-allocate, this removes the * Dcache aliasing issue. The writes will be forwarded to the write buffer, * and merged as appropriate. * * Note: We rely on all ARMv4 processors implementing the "invalidate D line" * instruction. If your processor does not supply this, you have to write your * own copy_user_page that does the right thing. */ ENTRY(v4_mc_copy_user_page) stmfd sp!, {r4, lr} @ 2 mov r4, r0 mov r0, r1 bl map_page_minicache mov r1, #PAGE_SZ/64 @ 1 ldmia r0!, {r2, r3, ip, lr} @ 4 1: mcr p15, 0, r4, c7, c6, 1 @ 1 invalidate D line stmia r4!, {r2, r3, ip, lr} @ 4 ldmia r0!, {r2, r3, ip, lr} @ 4+1 stmia r4!, {r2, r3, ip, lr} @ 4 ldmia r0!, {r2, r3, ip, lr} @ 4 mcr p15, 0, r4, c7, c6, 1 @ 1 invalidate D line stmia r4!, {r2, r3, ip, lr} @ 4 ldmia r0!, {r2, r3, ip, lr} @ 4 subs r1, r1, #1 @ 1 stmia r4!, {r2, r3, ip, lr} @ 4 ldmneia r0!, {r2, r3, ip, lr} @ 4 bne 1b @ 1 ldmfd sp!, {r4, pc} @ 3 .align 5 /* * ARMv4 optimised clear_user_page * * Same story as above. */ ENTRY(v4_mc_clear_user_page) str lr, [sp, #-4]! mov r1, #PAGE_SZ/64 @ 1 mov r2, #0 @ 1 mov r3, #0 @ 1 mov ip, #0 @ 1 mov lr, #0 @ 1 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line stmia r0!, {r2, r3, ip, lr} @ 4 stmia r0!, {r2, r3, ip, lr} @ 4 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line stmia r0!, {r2, r3, ip, lr} @ 4 stmia r0!, {r2, r3, ip, lr} @ 4 subs r1, r1, #1 @ 1 bne 1b @ 1 ldr pc, [sp], #4 __INITDATA .type v4_mc_user_fns, #object ENTRY(v4_mc_user_fns) .long v4_mc_clear_user_page .long v4_mc_copy_user_page .size v4_mc_user_fns, . - v4_mc_user_fns
arch/arm/mm/copypage-v4mc.c 0 → 100644 +111 −0 Original line number Diff line number Diff line /* * linux/arch/arm/lib/copypage-armv4mc.S * * Copyright (C) 1995-2005 Russell King * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This handles the mini data cache, as found on SA11x0 and XScale * processors. When we copy a user page page, we map it in such a way * that accesses to this page will not touch the main data cache, but * will be cached in the mini data cache. This prevents us thrashing * the main data cache on page faults. */ #include <linux/init.h> #include <linux/mm.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> /* * 0xffff8000 to 0xffffffff is reserved for any ARM architecture * specific hacks for copying pages efficiently. */ #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ L_PTE_CACHEABLE) #define TOP_PTE(x) pte_offset_kernel(top_pmd, x) static DEFINE_SPINLOCK(minicache_lock); /* * ARMv4 mini-dcache optimised copy_user_page * * We flush the destination cache lines just before we write the data into the * corresponding address. Since the Dcache is read-allocate, this removes the * Dcache aliasing issue. The writes will be forwarded to the write buffer, * and merged as appropriate. * * Note: We rely on all ARMv4 processors implementing the "invalidate D line" * instruction. If your processor does not supply this, you have to write your * own copy_user_page that does the right thing. */ static void __attribute__((naked)) mc_copy_user_page(void *from, void *to) { asm volatile( "stmfd sp!, {r4, lr} @ 2\n\ mov r4, %2 @ 1\n\ ldmia %0!, {r2, r3, ip, lr} @ 4\n\ 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ stmia %1!, {r2, r3, ip, lr} @ 4\n\ ldmia %0!, {r2, r3, ip, lr} @ 4+1\n\ stmia %1!, {r2, r3, ip, lr} @ 4\n\ ldmia %0!, {r2, r3, ip, lr} @ 4\n\ mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ stmia %1!, {r2, r3, ip, lr} @ 4\n\ ldmia %0!, {r2, r3, ip, lr} @ 4\n\ subs r4, r4, #1 @ 1\n\ stmia %1!, {r2, r3, ip, lr} @ 4\n\ ldmneia %0!, {r2, r3, ip, lr} @ 4\n\ bne 1b @ 1\n\ ldmfd sp!, {r4, pc} @ 3" : : "r" (from), "r" (to), "I" (PAGE_SIZE / 64)); } void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr) { spin_lock(&minicache_lock); set_pte(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot)); flush_tlb_kernel_page(0xffff8000); mc_copy_user_page((void *)0xffff8000, kto); spin_unlock(&minicache_lock); } /* * ARMv4 optimised clear_user_page */ void __attribute__((naked)) v4_mc_clear_user_page(void *kaddr, unsigned long vaddr) { asm volatile( "str lr, [sp, #-4]!\n\ mov r1, %0 @ 1\n\ mov r2, #0 @ 1\n\ mov r3, #0 @ 1\n\ mov ip, #0 @ 1\n\ mov lr, #0 @ 1\n\ 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ stmia r0!, {r2, r3, ip, lr} @ 4\n\ stmia r0!, {r2, r3, ip, lr} @ 4\n\ mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ stmia r0!, {r2, r3, ip, lr} @ 4\n\ stmia r0!, {r2, r3, ip, lr} @ 4\n\ subs r1, r1, #1 @ 1\n\ bne 1b @ 1\n\ ldr pc, [sp], #4" : : "I" (PAGE_SIZE / 64)); } struct cpu_user_fns v4_mc_user_fns __initdata = { .cpu_clear_user_page = v4_mc_clear_user_page, .cpu_copy_user_page = v4_mc_copy_user_page, };
