Commit 695c5d3a authored by Jun ASAKA's avatar Jun ASAKA Committed by Kalle Valo
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wifi: rtl8xxxu: fixing IQK failures for rtl8192eu 

Fixing "Path A RX IQK failed" and "Path B RX IQK failed"
issues for rtl8192eu chips by replacing the arguments with
the ones in the updated official driver as shown below.
1. https://github.com/Mange/rtl8192eu-linux-driver


2. vendor driver version: 5.6.4

Signed-off-by: default avatarJun ASAKA <JunASAKA@zzy040330.moe>
Reviewed-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20221207033926.11777-1-JunASAKA@zzy040330.moe
parent e48c4531

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c

+51 −22
Original line number Diff line number Diff line
@@ -780,6 +780,12 @@ static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) 
	 */

	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180);



	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07f77);



	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);



	/* Path A IQK setting */
@@ -825,11 +831,16 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) 
	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);



	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173);



	/* PA/PAD control by 0x56, and set = 0x0 */

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x511e0);



	/* Enter IQK mode */

	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
@@ -844,14 +855,14 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) 
	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);

	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);



	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);

	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f);

	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216031f);

	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x6816031f);



	/* LO calibration setting */

	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);



	/* One shot, path A LOK & IQK */

	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);

	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);

	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);



	mdelay(10);
@@ -882,11 +893,16 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) 
	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2);



	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2);



	/* PA/PAD control by 0x56, and set = 0x0 */

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x510e0);



	/* Enter IQK mode */

	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
@@ -900,14 +916,14 @@ static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) 
	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);

	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);



	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);

	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);

	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff);

	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff);



	/* LO calibration setting */

	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);



	/* One shot, path A LOK & IQK */

	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);

	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);

	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);



	mdelay(10);
@@ -937,9 +953,12 @@ static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) 


	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180);

	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);



	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0x07f77);



	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);



	/* Path B IQK setting */
@@ -948,11 +967,11 @@ static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) 
	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);

	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);



	rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2);

	rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140303);

	rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000);



	/* LO calibration setting */

	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911);

	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);



	/* One shot, path A LOK & IQK */

	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
@@ -988,11 +1007,16 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) 
	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173);



	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);



	/* PA/PAD control by 0x56, and set = 0x0 */

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x511e0);



	/* Enter IQK mode */

	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
@@ -1007,8 +1031,8 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) 
	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);

	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);



	rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f);

	rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f);

	rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8216031f);

	rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x6816031f);



	/* LO calibration setting */

	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
@@ -1048,11 +1072,16 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) 
	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2);



	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);

	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2);



	/* PA/PAD control by 0x56, and set = 0x0 */

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);

	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x510e0);



	/* Enter IQK mode */

	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
@@ -1066,8 +1095,8 @@ static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) 
	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);

	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);



	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);

	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);

	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff);

	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff);



	/* LO calibration setting */

	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);