Loading drivers/edac/amd64_edac.h +8 −35 Original line number Diff line number Diff line Loading @@ -244,44 +244,17 @@ #define F10_DCTL_SEL_LOW 0x110 #define dct_sel_baseaddr(pvt) \ ((pvt->dram_ctl_select_low) & 0xFFFFF800) #define dct_sel_interleave_addr(pvt) \ (((pvt->dram_ctl_select_low) >> 6) & 0x3) enum { F10_DCTL_SEL_LOW_DctSelHiRngEn = BIT(0), F10_DCTL_SEL_LOW_DctSelIntLvEn = BIT(2), F10_DCTL_SEL_LOW_DctGangEn = BIT(4), F10_DCTL_SEL_LOW_DctDatIntLv = BIT(5), F10_DCTL_SEL_LOW_DramEnable = BIT(8), F10_DCTL_SEL_LOW_MemCleared = BIT(10), }; #define dct_high_range_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelHiRngEn) #define dct_interleave_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelIntLvEn) #define dct_ganging_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctGangEn) #define dct_data_intlv_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctDatIntLv) #define dct_dram_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DramEnable) #define dct_memory_cleared(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_MemCleared) #define dct_sel_baseaddr(pvt) ((pvt->dram_ctl_select_low) & 0xFFFFF800) #define dct_sel_interleave_addr(pvt) (((pvt->dram_ctl_select_low) >> 6) & 0x3) #define dct_high_range_enabled(pvt) (pvt->dram_ctl_select_low & BIT(0)) #define dct_interleave_enabled(pvt) (pvt->dram_ctl_select_low & BIT(2)) #define dct_ganging_enabled(pvt) (pvt->dram_ctl_select_low & BIT(4)) #define dct_data_intlv_enabled(pvt) (pvt->dram_ctl_select_low & BIT(5)) #define dct_dram_enabled(pvt) (pvt->dram_ctl_select_low & BIT(8)) #define dct_memory_cleared(pvt) (pvt->dram_ctl_select_low & BIT(10)) #define F10_DCTL_SEL_HIGH 0x114 /* * Function 3 - Misc Control */ Loading Loading
drivers/edac/amd64_edac.h +8 −35 Original line number Diff line number Diff line Loading @@ -244,44 +244,17 @@ #define F10_DCTL_SEL_LOW 0x110 #define dct_sel_baseaddr(pvt) \ ((pvt->dram_ctl_select_low) & 0xFFFFF800) #define dct_sel_interleave_addr(pvt) \ (((pvt->dram_ctl_select_low) >> 6) & 0x3) enum { F10_DCTL_SEL_LOW_DctSelHiRngEn = BIT(0), F10_DCTL_SEL_LOW_DctSelIntLvEn = BIT(2), F10_DCTL_SEL_LOW_DctGangEn = BIT(4), F10_DCTL_SEL_LOW_DctDatIntLv = BIT(5), F10_DCTL_SEL_LOW_DramEnable = BIT(8), F10_DCTL_SEL_LOW_MemCleared = BIT(10), }; #define dct_high_range_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelHiRngEn) #define dct_interleave_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctSelIntLvEn) #define dct_ganging_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctGangEn) #define dct_data_intlv_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DctDatIntLv) #define dct_dram_enabled(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_DramEnable) #define dct_memory_cleared(pvt) \ (pvt->dram_ctl_select_low & F10_DCTL_SEL_LOW_MemCleared) #define dct_sel_baseaddr(pvt) ((pvt->dram_ctl_select_low) & 0xFFFFF800) #define dct_sel_interleave_addr(pvt) (((pvt->dram_ctl_select_low) >> 6) & 0x3) #define dct_high_range_enabled(pvt) (pvt->dram_ctl_select_low & BIT(0)) #define dct_interleave_enabled(pvt) (pvt->dram_ctl_select_low & BIT(2)) #define dct_ganging_enabled(pvt) (pvt->dram_ctl_select_low & BIT(4)) #define dct_data_intlv_enabled(pvt) (pvt->dram_ctl_select_low & BIT(5)) #define dct_dram_enabled(pvt) (pvt->dram_ctl_select_low & BIT(8)) #define dct_memory_cleared(pvt) (pvt->dram_ctl_select_low & BIT(10)) #define F10_DCTL_SEL_HIGH 0x114 /* * Function 3 - Misc Control */ Loading