Commit 6917b0b7 authored by Martin Tsai's avatar Martin Tsai Committed by Alex Deucher
Browse files

drm/amd/display: Read down-spread percentage from lut to adjust dprefclk. 



[Why]
Panels show corruption with high refresh rate timings when
ss is enabled.

[How]
Read down-spread percentage from lut to adjust dprefclk.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarMartin Tsai <martin.tsai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 95aafbc1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

+31 −2
Original line number Diff line number Diff line
@@ -87,6 +87,14 @@ static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 
#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK	0x0000F000L

#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK	0xFFFF0000L



#define regCLK1_CLK2_BYPASS_CNTL			0x029c

#define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX	0



#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT	0x0

#define CLK1_CLK2_BYPASS_CNTL__LK2_BYPASS_DIV__SHIFT	0x10

#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK		0x00000007L

#define CLK1_CLK2_BYPASS_CNTL__LK2_BYPASS_DIV_MASK		0x000F0000L



#define REG(reg_name) \

	(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
@@ -436,6 +444,11 @@ static DpmClocks314_t dummy_clocks; 


static struct dcn314_watermarks dummy_wms = { 0 };



static struct dcn314_ss_info_table ss_info_table = {

	.ss_divider = 1000,

	.ss_percentage = {0, 0, 375, 375, 375}

};



static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table)

{

	int i, num_valid_sets;
@@ -715,6 +728,20 @@ static struct clk_mgr_funcs dcn314_funcs = { 
};

extern struct clk_mgr_funcs dcn3_fpga_funcs;



static void dcn314_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)

{

	uint32_t clock_source;



	REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source);



	clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];



	if (clk_mgr->dprefclk_ss_percentage != 0) {

		clk_mgr->ss_on_dprefclk = true;

		clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;

	}

}



void dcn314_clk_mgr_construct(

		struct dc_context *ctx,

		struct clk_mgr_dcn314 *clk_mgr,
@@ -781,9 +808,11 @@ void dcn314_clk_mgr_construct( 


	clk_mgr->base.base.dprefclk_khz = 600000;

	clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;

	dce_clock_read_ss_info(&clk_mgr->base);



	dcn314_read_ss_info_from_lut(&clk_mgr->base);

	/*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/

	//clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);

	clk_mgr->base.base.dprefclk_khz =

		dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);



	clk_mgr->base.base.bw_params = &dcn314_bw_params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

+7 −0
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 
#define __DCN314_CLK_MGR_H__

#include "clk_mgr_internal.h"



#define NUM_CLOCK_SOURCES   5



struct dcn314_watermarks;



struct dcn314_smu_watermark_set {
@@ -40,6 +42,11 @@ struct clk_mgr_dcn314 { 
	struct dcn314_smu_watermark_set smu_wm_set;

};



struct dcn314_ss_info_table {

	uint32_t ss_divider;

	uint32_t ss_percentage[NUM_CLOCK_SOURCES];

};



bool dcn314_are_clock_states_equal(struct dc_clocks *a,

		struct dc_clocks *b);