Commit 691521a3 authored by Jacky Huang's avatar Jacky Huang Committed by Arnd Bergmann
Browse files

clk: nuvoton: Add clock driver for ma35d1 clock controller 



The clock controller generates clocks for the whole chip, including
system clocks and all peripheral clocks. This driver support ma35d1
clock gating, divider, and individual PLL configuration.

There are 6 PLLs in ma35d1 SoC:
  - CA-PLL for the two Cortex-A35 CPU clock
  - SYS-PLL for system bus, which comes from the companion MCU
    and cannot be programmed by clock controller.
  - DDR-PLL for DDR
  - EPLL for GMAC and GFX, Display, and VDEC IPs.
  - VPLL for video output pixel clock
  - APLL for SDHC, I2S audio, and other IPs.
CA-PLL has only one operation mode.
DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3
operation modes: integer mode, fraction mode, and spread specturm mode.

Signed-off-by: default avatarJacky Huang <ychuang3@nuvoton.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent b69af098

drivers/clk/Kconfig

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@@ -478,6 +478,7 @@ source "drivers/clk/meson/Kconfig" 
source "drivers/clk/mstar/Kconfig"

source "drivers/clk/microchip/Kconfig"

source "drivers/clk/mvebu/Kconfig"

source "drivers/clk/nuvoton/Kconfig"

source "drivers/clk/pistachio/Kconfig"

source "drivers/clk/qcom/Kconfig"

source "drivers/clk/ralink/Kconfig"

drivers/clk/Makefile

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@@ -106,6 +106,7 @@ endif 
obj-y					+= mstar/

obj-y					+= mvebu/

obj-$(CONFIG_ARCH_MXS)			+= mxs/

obj-$(CONFIG_ARCH_MA35)			+= nuvoton/

obj-$(CONFIG_COMMON_CLK_NXP)		+= nxp/

obj-$(CONFIG_COMMON_CLK_PISTACHIO)	+= pistachio/

obj-$(CONFIG_COMMON_CLK_PXA)		+= pxa/

drivers/clk/nuvoton/Kconfig

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# SPDX-License-Identifier: GPL-2.0

# common clock support for Nuvoton SoC family.



config COMMON_CLK_NUVOTON

	bool "Nuvoton clock controller common support"

	depends on ARCH_MA35 || COMPILE_TEST

	default y

	help

	  Say y here to enable common clock controller for Nuvoton platforms.



if COMMON_CLK_NUVOTON



config CLK_MA35D1

	bool "Nuvoton MA35D1 clock controller support"

	default y

	help

	  Build the clock controller driver for MA35D1 SoC.



endif

drivers/clk/nuvoton/Makefile

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# SPDX-License-Identifier: GPL-2.0-only

obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1.o

obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-divider.o

obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-pll.o

drivers/clk/nuvoton/clk-ma35d1-divider.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (C) 2023 Nuvoton Technology Corp.

 * Author: Chi-Fang Li <cfli0@nuvoton.com>

 */



#include <linux/clk-provider.h>

#include <linux/device.h>

#include <linux/regmap.h>

#include <linux/spinlock.h>



struct ma35d1_adc_clk_div {

	struct clk_hw hw;

	void __iomem *reg;

	u8 shift;

	u8 width;

	u32 mask;

	const struct clk_div_table *table;

	/* protects concurrent access to clock divider registers */

	spinlock_t *lock;

};



struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,

				     struct clk_hw *parent_hw, spinlock_t *lock,

				     unsigned long flags, void __iomem *reg,

				     u8 shift, u8 width, u32 mask_bit);



static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw)

{

	return container_of(_hw, struct ma35d1_adc_clk_div, hw);

}



static unsigned long ma35d1_clkdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{

	unsigned int val;

	struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);



	val = readl_relaxed(dclk->reg) >> dclk->shift;

	val &= clk_div_mask(dclk->width);

	val += 1;

	return divider_recalc_rate(hw, parent_rate, val, dclk->table,

				   CLK_DIVIDER_ROUND_CLOSEST, dclk->width);

}



static long ma35d1_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)

{

	struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);



	return divider_round_rate(hw, rate, prate, dclk->table,

				  dclk->width, CLK_DIVIDER_ROUND_CLOSEST);

}



static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)

{

	int value;

	unsigned long flags = 0;

	u32 data;

	struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);



	value = divider_get_val(rate, parent_rate, dclk->table,

				dclk->width, CLK_DIVIDER_ROUND_CLOSEST);



	spin_lock_irqsave(dclk->lock, flags);



	data = readl_relaxed(dclk->reg);

	data &= ~(clk_div_mask(dclk->width) << dclk->shift);

	data |= (value - 1) << dclk->shift;

	data |= dclk->mask;

	writel_relaxed(data, dclk->reg);



	spin_unlock_irqrestore(dclk->lock, flags);

	return 0;

}



static const struct clk_ops ma35d1_adc_clkdiv_ops = {

	.recalc_rate = ma35d1_clkdiv_recalc_rate,

	.round_rate = ma35d1_clkdiv_round_rate,

	.set_rate = ma35d1_clkdiv_set_rate,

};



struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,

				     struct clk_hw *parent_hw, spinlock_t *lock,

				     unsigned long flags, void __iomem *reg,

				     u8 shift, u8 width, u32 mask_bit)

{

	struct ma35d1_adc_clk_div *div;

	struct clk_init_data init;

	struct clk_div_table *table;

	struct clk_parent_data pdata = { .index = 0 };

	u32 max_div, min_div;

	struct clk_hw *hw;

	int ret;

	int i;



	div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);

	if (!div)

		return ERR_PTR(-ENOMEM);



	max_div = clk_div_mask(width) + 1;

	min_div = 1;



	table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL);

	if (!table)

		return ERR_PTR(-ENOMEM);



	for (i = 0; i < max_div; i++) {

		table[i].val = min_div + i;

		table[i].div = 2 * table[i].val;

	}

	table[max_div].val = 0;

	table[max_div].div = 0;



	memset(&init, 0, sizeof(init));

	init.name = name;

	init.ops = &ma35d1_adc_clkdiv_ops;

	init.flags |= flags;

	pdata.hw = parent_hw;

	init.parent_data = &pdata;

	init.num_parents = 1;



	div->reg = reg;

	div->shift = shift;

	div->width = width;

	div->mask = mask_bit ? BIT(mask_bit) : 0;

	div->lock = lock;

	div->hw.init = &init;

	div->table = table;



	hw = &div->hw;

	ret = devm_clk_hw_register(dev, hw);

	if (ret)

		return ERR_PTR(ret);

	return hw;

}

EXPORT_SYMBOL_GPL(ma35d1_reg_adc_clkdiv);