Commit 690a757d authored by Jing Liu's avatar Jing Liu Committed by Paolo Bonzini
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kvm: x86: Add CPUID support for Intel AMX 



Extend CPUID emulation to support XFD, AMX_TILE, AMX_INT8 and
AMX_BF16. Adding those bits into kvm_cpu_caps finally activates all
previous logics in this series.

Hide XFD on 32bit host kernels. Otherwise it leads to a weird situation
where KVM tells userspace to migrate MSR_IA32_XFD and then rejects
attempts to read/write the MSR.

Signed-off-by: default avatarJing Liu <jing2.liu@intel.com>
Signed-off-by: default avatarYang Zhong <yang.zhong@intel.com>
Message-Id: <20220105123532.12586-17-yang.zhong@intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 86aff7a4

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Diff line number Diff line
@@ -299,7 +299,9 @@ 
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */

#define X86_FEATURE_AMX_BF16		(18*32+22) /* AMX bf16 Support */

#define X86_FEATURE_AMX_TILE		(18*32+24) /* AMX tile Support */

#define X86_FEATURE_AMX_INT8		(18*32+25) /* AMX int8 Support */



/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

arch/x86/kvm/cpuid.c

+25 −2
Original line number Diff line number Diff line
@@ -442,9 +442,11 @@ void kvm_set_cpu_caps(void) 
#ifdef CONFIG_X86_64

	unsigned int f_gbpages = F(GBPAGES);

	unsigned int f_lm = F(LM);

	unsigned int f_xfd = F(XFD);

#else

	unsigned int f_gbpages = 0;

	unsigned int f_lm = 0;

	unsigned int f_xfd = 0;

#endif

	memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps));
@@ -512,7 +514,8 @@ void kvm_set_cpu_caps(void) 
		F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |

		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |

		F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |

		F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16)

		F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |

		F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16)

	);



	/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
@@ -531,7 +534,7 @@ void kvm_set_cpu_caps(void) 
	);



	kvm_cpu_cap_mask(CPUID_D_1_EAX,

		F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES)

		F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd

	);



	kvm_cpu_cap_init_scattered(CPUID_12_EAX,
@@ -657,6 +660,8 @@ static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 
	case 0x14:

	case 0x17:

	case 0x18:

	case 0x1d:

	case 0x1e:

	case 0x1f:

	case 0x8000001d:

		entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
@@ -929,6 +934,24 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 
				goto out;

		}

		break;

	/* Intel AMX TILE */

	case 0x1d:

		if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {

			entry->eax = entry->ebx = entry->ecx = entry->edx = 0;

			break;

		}



		for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {

			if (!do_host_cpuid(array, function, i))

				goto out;

		}

		break;

	case 0x1e: /* TMUL information */

		if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) {

			entry->eax = entry->ebx = entry->ecx = entry->edx = 0;

			break;

		}

		break;

	case KVM_CPUID_SIGNATURE: {

		const u32 *sigptr = (const u32 *)KVM_SIGNATURE;

		entry->eax = KVM_CPUID_FEATURES;