Commit 68fce5f0 authored Dec 08, 2020 by Nirmoy Das Committed by Alex Deucher Dec 08, 2020

drm/amdgpu: use AMDGPU_NUM_VMID when possible



Replace hardcoded vmid number with AMDGPU_NUM_VMID macro.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 92c415a3

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -4844,7 +4844,7 @@ static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
		* the driver can enable them for graphics. VMID0 should maintain
		* access so that HWS firmware can save/restore entries.
		*/
		for (vmid = 1; vmid < 16; vmid++) {
		for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1896,7 +1896,7 @@ static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
		* the driver can enable them for graphics. VMID0 should maintain
		* access so that HWS firmware can save/restore entries.
		*/
		for (vmid = 1; vmid < 16; vmid++) {
		for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
		WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
		WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
		WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -3749,7 +3749,7 @@ static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
		* the driver can enable them for graphics. VMID0 should maintain
		* access so that HWS firmware can save/restore entries.
		*/
		for (vmid = 1; vmid < 16; vmid++) {
		for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
		WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
		WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
		WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -2520,7 +2520,7 @@ static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
		* the driver can enable them for graphics. VMID0 should maintain
		* access so that HWS firmware can save/restore entries.
		*/
		for (vmid = 1; vmid < 16; vmid++) {
		for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -432,7 +432,7 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
		return 0;
		}

		for (vmid = 1; vmid < 16; vmid++) {
		for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {

		ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
		&queried_pasid);