Commit 68fc5990 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: OMAP2+: Drop legacy remaining legacy platform data for am3 



We can now drop the remaining legacy platform data as we are
probing devices with device tree data.

Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 472931c6

arch/arm/mach-omap2/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -205,7 +205,6 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o 
obj-$(CONFIG_SOC_OMAP2430)		+= omap_hwmod_2430_data.o

obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_ipblock_data.o

obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_3xxx_data.o

obj-$(CONFIG_SOC_AM33XX)		+= omap_hwmod_33xx_data.o

obj-$(CONFIG_SOC_AM33XX)		+= omap_hwmod_33xx_43xx_interconnect_data.o

obj-$(CONFIG_SOC_AM33XX)		+= omap_hwmod_33xx_43xx_ipblock_data.o

obj-$(CONFIG_SOC_AM43XX)		+= omap_hwmod_43xx_data.o

arch/arm/mach-omap2/io.c

+0 −2
Original line number Diff line number Diff line
@@ -567,8 +567,6 @@ void __init am33xx_init_early(void) 
	omap2_prcm_base_init();

	am33xx_powerdomains_init();

	am33xx_clockdomains_init();

	am33xx_hwmod_init();

	omap_hwmod_init_postsetup();

	omap_clk_soc_init = am33xx_dt_clk_init;

	omap_secure_init();

}

arch/arm/mach-omap2/omap_hwmod_33xx_data.c

deleted100644 → 0
+0 −161
Original line number Diff line number Diff line 
/*

 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips

 *

 * Copyright (C) {2012} Texas Instruments Incorporated - https://www.ti.com/

 *

 * This file is automatically generated from the AM33XX hardware databases.

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any

 * kind, whether express or implied; without even the implied warranty

 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 */



#include "omap_hwmod.h"

#include "omap_hwmod_common_data.h"



#include "control.h"

#include "cm33xx.h"

#include "prm33xx.h"

#include "prm-regbits-33xx.h"

#include "omap_hwmod_33xx_43xx_common_data.h"



/*

 * IP blocks

 */



/* l4_hs */

static struct omap_hwmod am33xx_l4_hs_hwmod = {

	.name		= "l4_hs",

	.class		= &am33xx_l4_hwmod_class,

	.clkdm_name	= "l4hs_clkdm",

	.flags		= HWMOD_INIT_NO_IDLE,

	.main_clk	= "l4hs_gclk",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



/*

 * Modules omap_hwmod structures

 *

 * The following IPs are excluded for the moment because:

 * - They do not need an explicit SW control using omap_hwmod API.

 * - They still need to be validated with the driver

 *   properly adapted to omap_hwmod / omap_device

 *

 *    - cEFUSE (doesn't fall under any ocp_if)

 *    - clkdiv32k

 *    - ocp watch point

 */

#if 0

/*

 * 'cefuse' class

 */

static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {

	.name		= "cefuse",

};



static struct omap_hwmod am33xx_cefuse_hwmod = {

	.name		= "cefuse",

	.class		= &am33xx_cefuse_hwmod_class,

	.clkdm_name	= "l4_cefuse_clkdm",

	.main_clk	= "cefuse_fck",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



/*

 * 'clkdiv32k' class

 */

static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {

	.name		= "clkdiv32k",

};



static struct omap_hwmod am33xx_clkdiv32k_hwmod = {

	.name		= "clkdiv32k",

	.class		= &am33xx_clkdiv32k_hwmod_class,

	.clkdm_name	= "clk_24mhz_clkdm",

	.main_clk	= "clkdiv32k_ick",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};



/* ocpwp */

static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {

	.name		= "ocpwp",

};



static struct omap_hwmod am33xx_ocpwp_hwmod = {

	.name		= "ocpwp",

	.class		= &am33xx_ocpwp_hwmod_class,

	.clkdm_name	= "l4ls_clkdm",

	.main_clk	= "l4ls_gclk",

	.prcm		= {

		.omap4	= {

			.clkctrl_offs	= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,

			.modulemode	= MODULEMODE_SWCTRL,

		},

	},

};

#endif



/*

 * Interfaces

 */



/* l3 main -> l4 hs */

static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {

	.master		= &am33xx_l3_main_hwmod,

	.slave		= &am33xx_l4_hs_hwmod,

	.clk		= "l3s_gclk",

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* l4 wkup -> smartreflex0 */

static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {

	.master		= &am33xx_l4_wkup_hwmod,

	.slave		= &am33xx_smartreflex0_hwmod,

	.clk		= "dpll_core_m4_div2_ck",

	.user		= OCP_USER_MPU,

};



/* l4 wkup -> smartreflex1 */

static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {

	.master		= &am33xx_l4_wkup_hwmod,

	.slave		= &am33xx_smartreflex1_hwmod,

	.clk		= "dpll_core_m4_div2_ck",

	.user		= OCP_USER_MPU,

};



static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {

	&am33xx_l3_s__l4_ls,

	&am33xx_l3_s__l4_wkup,

	&am33xx_l3_main__l4_hs,

	&am33xx_l3_main__l3_s,

	&am33xx_l3_s__l3_main,

	&am33xx_l4_wkup__smartreflex0,

	&am33xx_l4_wkup__smartreflex1,

	NULL,

};



int __init am33xx_hwmod_init(void)

{

	omap_hwmod_am33xx_reg();

	omap_hwmod_init();

	return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);

}