Commit 68fa55f0 authored by Bharat Bhushan's avatar Bharat Bhushan Committed by Will Deacon
Browse files

perf/marvell: cn10k DDR perf event core ownership 



As DDR perf event counters are not per core, so they should be accessed
only by one core at a time. Select new core when previously owning core
is going offline.

Signed-off-by: default avatarBharat Bhushan <bbhushan2@marvell.com>
Reviewed-by: default avatarBhaskara Budiredla <bbudiredla@marvell.com>
Link: https://lore.kernel.org/r/20220211045346.17894-5-bbhushan2@marvell.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 35a43326

drivers/perf/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -148,4 +148,11 @@ config MARVELL_CN10K_TAD_PMU 


source "drivers/perf/hisilicon/Kconfig"



config MARVELL_CN10K_DDR_PMU

	tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"

	depends on ARM64 || (COMPILE_TEST && 64BIT)

	help

	  Enable perf support for Marvell DDR Performance monitoring

	  event on CN10K platform.



endmenu

drivers/perf/marvell_cn10k_ddr_pmu.c

+48 −2
Original line number Diff line number Diff line
@@ -129,6 +129,7 @@ struct cn10k_ddr_pmu { 
	int active_events;

	struct perf_event *events[DDRC_PERF_NUM_COUNTERS];

	struct hrtimer hrtimer;

	struct hlist_node node;

};



#define to_cn10k_ddr_pmu(p)	container_of(p, struct cn10k_ddr_pmu, pmu)
@@ -610,6 +611,24 @@ static enum hrtimer_restart cn10k_ddr_pmu_timer_handler(struct hrtimer *hrtimer) 
	return HRTIMER_RESTART;

}



static int cn10k_ddr_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)

{

	struct cn10k_ddr_pmu *pmu = hlist_entry_safe(node, struct cn10k_ddr_pmu,

						     node);

	unsigned int target;



	if (cpu != pmu->cpu)

		return 0;



	target = cpumask_any_but(cpu_online_mask, cpu);

	if (target >= nr_cpu_ids)

		return 0;



	perf_pmu_migrate_context(&pmu->pmu, cpu, target);

	pmu->cpu = target;

	return 0;

}



static int cn10k_ddr_perf_probe(struct platform_device *pdev)

{

	struct cn10k_ddr_pmu *ddr_pmu;
@@ -661,18 +680,31 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev) 
	hrtimer_init(&ddr_pmu->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);

	ddr_pmu->hrtimer.function = cn10k_ddr_pmu_timer_handler;



	cpuhp_state_add_instance_nocalls(

				CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,

				&ddr_pmu->node);



	ret = perf_pmu_register(&ddr_pmu->pmu, name, -1);

	if (ret)

		return ret;

		goto error;



	pr_info("CN10K DDR PMU Driver for ddrc@%llx\n", res->start);

	return 0;

error:

	cpuhp_state_remove_instance_nocalls(

				CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,

				&ddr_pmu->node);

	return ret;

}



static int cn10k_ddr_perf_remove(struct platform_device *pdev)

{

	struct cn10k_ddr_pmu *ddr_pmu = platform_get_drvdata(pdev);



	cpuhp_state_remove_instance_nocalls(

				CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,

				&ddr_pmu->node);



	perf_pmu_unregister(&ddr_pmu->pmu);

	return 0;

}
@@ -697,12 +729,26 @@ static struct platform_driver cn10k_ddr_pmu_driver = { 


static int __init cn10k_ddr_pmu_init(void)

{

	return platform_driver_register(&cn10k_ddr_pmu_driver);

	int ret;



	ret = cpuhp_setup_state_multi(

				CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,

				"perf/marvell/cn10k/ddr:online", NULL,

				cn10k_ddr_pmu_offline_cpu);

	if (ret)

		return ret;



	ret = platform_driver_register(&cn10k_ddr_pmu_driver);

	if (ret)

		cpuhp_remove_multi_state(

				CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE);

	return ret;

}



static void __exit cn10k_ddr_pmu_exit(void)

{

	platform_driver_unregister(&cn10k_ddr_pmu_driver);

	cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE);

}



module_init(cn10k_ddr_pmu_init);

include/linux/cpuhotplug.h

+1 −0
Original line number Diff line number Diff line
@@ -231,6 +231,7 @@ enum cpuhp_state { 
	CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,

	CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,

	CPUHP_AP_PERF_ARM_CAVIUM_TX2_UNCORE_ONLINE,

	CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,

	CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,

	CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,

	CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,