Commit 68f863e5 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
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clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clock 



This clock enables the GPLL0 output to the multimedia subsystem
clock controller.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210114221059.483390-3-angelogioacchino.delregno@somainline.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 68e5d392

drivers/clk/qcom/gcc-msm8998.c

+17 −0
Original line number Diff line number Diff line
@@ -1341,6 +1341,22 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { 
	},

};



static struct clk_branch gcc_mmss_gpll0_clk = {

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(1),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_mmss_gpll0_clk",

			.parent_names = (const char *[]){

				"gpll0_out_main",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_mss_gpll0_div_clk_src = {

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {
@@ -2944,6 +2960,7 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { 
	[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,

	[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,

	[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,

	[GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,

};



static struct gdsc *gcc_msm8998_gdscs[] = {