Unverified Commit 68edb53a authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-5.19-soc' of... 

Merge tag 'tegra-for-5.19-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

soc/tegra: Changes for v5.19-rc1

This set of changes adds nvmem cell lookup entries for Tegra194 that are
used to read calibration data from the SoC fuses, and updates the reset
sources for Tegra234.

Other than that, included is a minor build fix for a missing dependency
that can be encountered very rarely in random config builds. Lastly some
kerneldoc comments are added to avoid build warnings.

* tag 'tegra-for-5.19-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Document core domain fields
  soc/tegra: pmc: Select REGMAP
  soc/tegra: pmc: Update Tegra234 reset sources
  soc/tegra: fuse: Add nvmem cell lookup entries for Tegra194

Link: https://lore.kernel.org/r/20220506143005.3916655-2-thierry.reding@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 819ed6f0 d3a20dcb

drivers/soc/tegra/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@ config SOC_TEGRA_PMC 
	select GENERIC_PINCONF

	select PM_OPP

	select PM_GENERIC_DOMAINS

	select REGMAP



config SOC_TEGRA_POWERGATE_BPMP

	def_bool y

drivers/soc/tegra/fuse/fuse-tegra.c

+4 −4
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013-2021, NVIDIA CORPORATION.  All rights reserved.

 * Copyright (c) 2013-2022, NVIDIA CORPORATION.  All rights reserved.

 */



#include <linux/clk.h>
@@ -162,7 +162,7 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { 
		.bit_offset = 0,

		.nbits = 32,

	}, {

		.name = "gcplex-config-fuse",

		.name = "gpu-gcplex-config-fuse",

		.offset = 0x1c8,

		.bytes = 4,

		.bit_offset = 0,
@@ -186,13 +186,13 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { 
		.bit_offset = 0,

		.nbits = 32,

	}, {

		.name = "pdi0",

		.name = "gpu-pdi0",

		.offset = 0x300,

		.bytes = 4,

		.bit_offset = 0,

		.nbits = 32,

	}, {

		.name = "pdi1",

		.name = "gpu-pdi1",

		.offset = 0x304,

		.bytes = 4,

		.bit_offset = 0,

drivers/soc/tegra/fuse/fuse-tegra30.c

+16 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.

 * Copyright (c) 2013-2022, NVIDIA CORPORATION.  All rights reserved.

 */



#include <linux/device.h>
@@ -344,6 +344,21 @@ static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { 
		.cell_name = "xusb-pad-calibration-ext",

		.dev_id = "3520000.padctl",

		.con_id = "calibration-ext",

	}, {

		.nvmem_name = "fuse",

		.cell_name = "gpu-gcplex-config-fuse",

		.dev_id = "17000000.gpu",

		.con_id = "gcplex-config-fuse",

	}, {

		.nvmem_name = "fuse",

		.cell_name = "gpu-pdi0",

		.dev_id = "17000000.gpu",

		.con_id = "pdi0",

	}, {

		.nvmem_name = "fuse",

		.cell_name = "gpu-pdi1",

		.dev_id = "17000000.gpu",

		.con_id = "pdi1",

	},

};

drivers/soc/tegra/pmc.c

+27 −8
Original line number Diff line number Diff line
@@ -394,6 +394,8 @@ struct tegra_pmc_soc { 
 * @domain: IRQ domain provided by the PMC

 * @irq: chip implementation for the IRQ domain

 * @clk_nb: pclk clock changes handler

 * @core_domain_state_synced: flag marking the core domain's state as synced

 * @core_domain_registered: flag marking the core domain as registered

 */

struct tegra_pmc {

	struct device *dev;
@@ -3766,7 +3768,7 @@ static const struct tegra_pmc_regs tegra234_pmc_regs = { 
};



static const char * const tegra234_reset_sources[] = {

	"SYS_RESET_N",

	"SYS_RESET_N",	/* 0x0 */

	"AOWDT",

	"BCCPLEXWDT",

	"BPMPWDT",
@@ -3774,19 +3776,36 @@ static const char * const tegra234_reset_sources[] = { 
	"SPEWDT",

	"APEWDT",

	"LCCPLEXWDT",

	"SENSOR",

	"AOTAG",

	"VFSENSOR",

	"SENSOR",	/* 0x8 */

	NULL,

	NULL,

	"MAINSWRST",

	"SC7",

	"HSM",

	"CSITE",

	NULL,

	"RCEWDT",

	"PVA0WDT",

	"PVA1WDT",

	"L1A_ASYNC",

	NULL,		/* 0x10 */

	NULL,

	NULL,

	"BPMPBOOT",

	"FUSECRC",

	"DCEWDT",

	"PSCWDT",

	"PSC",

	"CSITE_SW",	/* 0x18 */

	"POD",

	"SCPM",

	"VREFRO_POWERBAD",

	"VMON",

	"FMON",

	"FSI_R5WDT",

	"FSI_THERM",

	"FSI_R52C0WDT",	/* 0x20 */

	"FSI_R52C1WDT",

	"FSI_R52C2WDT",

	"FSI_R52C3WDT",

	"FSI_FMON",

	"FSI_VMON",	/* 0x25 */

};



static const struct tegra_wake_event tegra234_wake_events[] = {