Commit 68daadf3 authored by Kent Russell's avatar Kent Russell Committed by Alex Deucher
Browse files

drm/amdgpu: Add kernel parameter support for ignoring bad page threshold



When a GPU hits the bad_page_threshold, it will not be initialized by
the amdgpu driver. This means that the table cannot be cleared, nor can
information gathering be performed (getting serial number, BDF, etc).

If the bad_page_threshold kernel parameter is set to -2,
continue to initialize the GPU, while printing a warning to dmesg that
this action has been done

v2: squash in Luben's fix to restore RAS info reporting

Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Mukul Joshi <Mukul.Joshi@amd.com>
Signed-off-by: default avatarKent Russell <kent.russell@amd.com>
Acked-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8483fdfe
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+1 −0
Original line number Diff line number Diff line
@@ -205,6 +205,7 @@ extern struct amdgpu_mgpu_info mgpu_info;
extern int amdgpu_ras_enable;
extern uint amdgpu_ras_mask;
extern int amdgpu_bad_page_threshold;
extern bool amdgpu_ignore_bad_page_threshold;
extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
extern int amdgpu_async_gfx_ring;
extern int amdgpu_mcbp;
+1 −1
Original line number Diff line number Diff line
@@ -877,7 +877,7 @@ module_param_named(reset_method, amdgpu_reset_method, int, 0444);
 * result in the GPU entering bad status when the number of total
 * faulty pages by ECC exceeds the threshold value.
 */
MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)");
MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);

MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
+11 −4
Original line number Diff line number Diff line
@@ -1104,6 +1104,12 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
				 ras->bad_page_cnt_threshold);
			res = amdgpu_ras_eeprom_correct_header_tag(control,
								   RAS_TABLE_HDR_VAL);
		} else {
			dev_err(adev->dev, "RAS records:%d exceed threshold:%d",
				control->ras_num_recs, ras->bad_page_cnt_threshold);
			if (amdgpu_bad_page_threshold == -2) {
				dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -2.");
				res = 0;
			} else {
				*exceed_err_limit = true;
				dev_err(adev->dev,
@@ -1111,6 +1117,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
					"GPU will not be initialized. Replace this GPU or increase the threshold",
					control->ras_num_recs, ras->bad_page_cnt_threshold);
			}
		}
	} else {
		DRM_INFO("Creating a new EEPROM table");