Commit 6894534b authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
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drm/amd/display: Enable timing sync on DCN32 



Missed enabling timing sync on DCN32 because DCN32 has a different DML
param.

Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 35fe1915

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+1 −0
Original line number Diff line number Diff line
@@ -1228,6 +1228,7 @@ int dcn20_populate_dml_pipes_from_context( 
		pipes[pipe_cnt].pipe.src.dcc = false;

		pipes[pipe_cnt].pipe.src.dcc_rate = 1;

		pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;

		pipes[pipe_cnt].pipe.dest.synchronize_timings = synchronized_vblank;

		pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;

		pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start

				- timing->h_addressable