Commit 6868fba5 authored by Hao Chen's avatar Hao Chen Committed by Jiantao Xiao
Browse files

net: hns3: add some link modes for hisilicon device 

mainline inclusion
from mainline-v6.7-rc1
commit 8ee2843f4d52026ab67e7577eaa49d444e1976b8
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8E4XS
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8ee2843f4d52026ab67e7577eaa49d444e1976b8



----------------------------------------------------------------------

Add HCLGE_SUPPORT_50G_R1_BIT and HCLGE_SUPPORT_100G_R2_BIT two
capability bits and Corresponding link modes.

Signed-off-by: default avatarHao Chen <chenhao418@huawei.com>
Signed-off-by: default avatarJijie Shao <shaojijie@huawei.com>
Reviewed-by: default avatarWojciech Drewek <wojciech.drewek@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarJiantao Xiao <xiaojiantao1@h-partners.com>
parent 90993e84

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+78 −80
Original line number Diff line number Diff line
@@ -946,8 +946,8 @@ static const struct hclge_speed_bit_map speed_bit_map[] = { 
	{HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT},

	{HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT},

	{HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},

	{HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT},

	{HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT},

	{HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS},

	{HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS},

	{HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},

};
@@ -1004,101 +1004,99 @@ static void hclge_update_fec_support(struct hclge_mac *mac) 
				 mac->supported);

}



static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[8] = {

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT},

	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT},

	{HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT},

	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},

};



static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[6] = {

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT},

	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT,

	 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT,

	 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT,

	 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},

};



static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[8] = {

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT},

	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT},

	{HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT},

	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},

};



static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[9] = {

	{HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},

	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT},

	{HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT},

	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},

};



static void hclge_convert_setting_sr(u16 speed_ability,

				     unsigned long *link_mode)

{

	if (speed_ability & HCLGE_SUPPORT_10G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_25G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_40G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_50G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_100G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_200G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,

	int i;



	for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) {

		if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit)

			linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode,

					 link_mode);

	}

}



static void hclge_convert_setting_lr(u16 speed_ability,

				     unsigned long *link_mode)

{

	if (speed_ability & HCLGE_SUPPORT_10G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_25G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_50G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_40G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_100G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_200G_BIT)

		linkmode_set_bit(

			ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,

	int i;



	for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) {

		if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit)

			linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode,

					 link_mode);

	}

}



static void hclge_convert_setting_cr(u16 speed_ability,

				     unsigned long *link_mode)

{

	if (speed_ability & HCLGE_SUPPORT_10G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_25G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_40G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_50G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_100G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_200G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,

	int i;



	for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) {

		if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit)

			linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode,

					 link_mode);

	}

}



static void hclge_convert_setting_kr(u16 speed_ability,

				     unsigned long *link_mode)

{

	if (speed_ability & HCLGE_SUPPORT_1G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_10G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_25G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_40G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_50G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_100G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,

				 link_mode);

	if (speed_ability & HCLGE_SUPPORT_200G_BIT)

		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,

	int i;



	for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) {

		if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit)

			linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode,

					 link_mode);

	}

}



static void hclge_convert_setting_fec(struct hclge_mac *mac)

{
@@ -1223,10 +1221,10 @@ static u32 hclge_get_max_speed(u16 speed_ability) 
	if (speed_ability & HCLGE_SUPPORT_200G_BIT)

		return HCLGE_MAC_SPEED_200G;



	if (speed_ability & HCLGE_SUPPORT_100G_BIT)

	if (speed_ability & HCLGE_SUPPORT_100G_BITS)

		return HCLGE_MAC_SPEED_100G;



	if (speed_ability & HCLGE_SUPPORT_50G_BIT)

	if (speed_ability & HCLGE_SUPPORT_50G_BITS)

		return HCLGE_MAC_SPEED_50G;



	if (speed_ability & HCLGE_SUPPORT_40G_BIT)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

+14 −2
Original line number Diff line number Diff line
@@ -189,15 +189,22 @@ enum HLCGE_PORT_TYPE { 
#define HCLGE_SUPPORT_1G_BIT		BIT(0)

#define HCLGE_SUPPORT_10G_BIT		BIT(1)

#define HCLGE_SUPPORT_25G_BIT		BIT(2)

#define HCLGE_SUPPORT_50G_BIT		BIT(3)

#define HCLGE_SUPPORT_100G_BIT		BIT(4)

#define HCLGE_SUPPORT_50G_R2_BIT	BIT(3)

#define HCLGE_SUPPORT_100G_R4_BIT	BIT(4)

/* to be compatible with exsit board */

#define HCLGE_SUPPORT_40G_BIT		BIT(5)

#define HCLGE_SUPPORT_100M_BIT		BIT(6)

#define HCLGE_SUPPORT_10M_BIT		BIT(7)

#define HCLGE_SUPPORT_200G_BIT		BIT(8)

#define HCLGE_SUPPORT_50G_R1_BIT	BIT(9)

#define HCLGE_SUPPORT_100G_R2_BIT	BIT(10)



#define HCLGE_SUPPORT_GE \

	(HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)

#define HCLGE_SUPPORT_50G_BITS \

	(HCLGE_SUPPORT_50G_R2_BIT | HCLGE_SUPPORT_50G_R1_BIT)

#define HCLGE_SUPPORT_100G_BITS \

	(HCLGE_SUPPORT_100G_R4_BIT | HCLGE_SUPPORT_100G_R2_BIT)



enum HCLGE_DEV_STATE {

	HCLGE_STATE_REINITING,
@@ -1112,6 +1119,11 @@ struct hclge_mac_speed_map { 
	u32 speed_fw; /* speed defined in firmware */

};



struct hclge_link_mode_bmap {

	u16 support_bit;

	enum ethtool_link_mode_bit_indices link_mode;

};



int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,

				 bool en_mc_pmc, bool en_bc_pmc);

int hclge_add_uc_addr_common(struct hclge_vport *vport,