Commit 6853fece authored Mar 09, 2022 by Tom Rix Committed by Rob Herring Mar 10, 2022

dt-bindings: clk: cleanup comments



For spdx, first line /* */ for *.h, change tab to space

Replacements
devider to divider
Comunications to Communications
periphrals to peripherals
supportted to supported
wich to which
Documentatoin to Documentation

Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220309222302.1114561-1-trix@redhat.com

parent b48b5636

include/dt-bindings/clock/alphascale,asm9260.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -55,7 +55,7 @@
		#define CLKID_AHB_I2S1 45
		#define CLKID_AHB_MAC1 46

		/* devider */
		/* divider */
		#define CLKID_SYS_CPU 47
		#define CLKID_SYS_AHB 48
		#define CLKID_SYS_I2S0M 49

include/dt-bindings/clock/axis,artpec6-clkctrl.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -2,7 +2,7 @@
		/*
		* ARTPEC-6 clock controller indexes
		*
		* Copyright 2016 Axis Comunications AB.
		* Copyright 2016 Axis Communications AB.
		*/

		#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H

include/dt-bindings/clock/boston-clock.h

+1 −2

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/*
		* Copyright (C) 2016 Imagination Technologies
		*
		* SPDX-License-Identifier: GPL-2.0
		*/

		#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__

include/dt-bindings/clock/marvell,mmp2.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -32,7 +32,7 @@
		#define MMP2_CLK_I2S0 31
		#define MMP2_CLK_I2S1 32

		/* apb periphrals */
		/* apb peripherals */
		#define MMP2_CLK_TWSI0 60
		#define MMP2_CLK_TWSI1 61
		#define MMP2_CLK_TWSI2 62
		@@ -60,7 +60,7 @@
		#define MMP3_CLK_THERMAL2 84
		#define MMP3_CLK_THERMAL3 85

		/* axi periphrals */
		/* axi peripherals */
		#define MMP2_CLK_SDH0 101
		#define MMP2_CLK_SDH1 102
		#define MMP2_CLK_SDH2 103

include/dt-bindings/clock/marvell,pxa168.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -23,7 +23,7 @@
		#define PXA168_CLK_UART_PLL 27
		#define PXA168_CLK_USB_PLL 28

		/* apb periphrals */
		/* apb peripherals */
		#define PXA168_CLK_TWSI0 60
		#define PXA168_CLK_TWSI1 61
		#define PXA168_CLK_TWSI2 62
		@@ -45,7 +45,7 @@
		#define PXA168_CLK_SSP4 78
		#define PXA168_CLK_TIMER 79

		/* axi periphrals */
		/* axi peripherals */
		#define PXA168_CLK_DFC 100
		#define PXA168_CLK_SDH0 101
		#define PXA168_CLK_SDH1 102