Commit 6825cfc9 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I
Browse files

phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz 



Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz
as specified in "Common Module Clock Configurations" of the Cadence
Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz
since the only user of Cadence Sierra SERDES, TI J721E SoC provides
input clock frequency of 100MHz. For other frequencies,
cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured
based on the "Common Module Clock Configurations".

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent a43f72ae

drivers/phy/cadence/phy-cadence-sierra.c

+21 −0
Original line number Diff line number Diff line
@@ -198,6 +198,8 @@ struct cdns_sierra_phy { 
	struct regmap_field *phy_pll_cfg_1;

	struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];

	struct clk *clk;

	struct clk *cmn_refclk_dig_div;

	struct clk *cmn_refclk1_dig_div;

	int nsubnodes;

	u32 num_lanes;

	bool autoconf;
@@ -279,6 +281,8 @@ static int cdns_sierra_phy_init(struct phy *gphy) 
	if (phy->autoconf)

		return 0;



	clk_set_rate(phy->cmn_refclk_dig_div, 25000000);

	clk_set_rate(phy->cmn_refclk1_dig_div, 25000000);

	if (ins->phy_type == PHY_TYPE_PCIE) {

		num_cmn_regs = phy->init_data->pcie_cmn_regs;

		num_ln_regs = phy->init_data->pcie_ln_regs;
@@ -468,6 +472,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) 
	struct resource *res;

	int i, ret, node = 0;

	void __iomem *base;

	struct clk *clk;

	struct device_node *dn = dev->of_node, *child;



	if (of_get_child_count(dn) == 0)
@@ -523,6 +528,22 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) 
		return PTR_ERR(sp->apb_rst);

	}



	clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");

	if (IS_ERR(clk)) {

		dev_err(dev, "cmn_refclk_dig_div clock not found\n");

		ret = PTR_ERR(clk);

		return ret;

	}

	sp->cmn_refclk_dig_div = clk;



	clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");

	if (IS_ERR(clk)) {

		dev_err(dev, "cmn_refclk1_dig_div clock not found\n");

		ret = PTR_ERR(clk);

		return ret;

	}

	sp->cmn_refclk1_dig_div = clk;



	ret = clk_prepare_enable(sp->clk);

	if (ret)

		return ret;