Loading drivers/pci/dmar.c +2 −1 Original line number Diff line number Diff line Loading @@ -806,7 +806,8 @@ int alloc_iommu(struct dmar_drhd_unit *drhd) } ver = readl(iommu->reg + DMAR_VER_REG); pr_info("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n", pr_info("IOMMU %d: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", iommu->seq_id, (unsigned long long)drhd->reg_base_addr, DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), (unsigned long long)iommu->cap, Loading drivers/pci/intel-iommu.c +6 −3 Original line number Diff line number Diff line Loading @@ -1150,7 +1150,8 @@ static int iommu_init_domains(struct intel_iommu *iommu) unsigned long nlongs; ndomains = cap_ndoms(iommu->cap); pr_debug("Number of Domains supportd <%ld>\n", ndomains); pr_debug("IOMMU %d: Number of Domains supportd <%ld>\n", iommu->seq_id, ndomains); nlongs = BITS_TO_LONGS(ndomains); spin_lock_init(&iommu->lock); Loading Loading @@ -2319,14 +2320,16 @@ int __init init_dmars(void) */ iommu->flush.flush_context = __iommu_flush_context; iommu->flush.flush_iotlb = __iommu_flush_iotlb; printk(KERN_INFO "IOMMU 0x%Lx: using Register based " printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based " "invalidation\n", iommu->seq_id, (unsigned long long)drhd->reg_base_addr); } else { iommu->flush.flush_context = qi_flush_context; iommu->flush.flush_iotlb = qi_flush_iotlb; printk(KERN_INFO "IOMMU 0x%Lx: using Queued " printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued " "invalidation\n", iommu->seq_id, (unsigned long long)drhd->reg_base_addr); } } Loading drivers/pci/intr_remapping.c +3 −3 Original line number Diff line number Diff line Loading @@ -832,8 +832,8 @@ static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, } printk(KERN_INFO "IOAPIC id %d under DRHD base " " 0x%Lx\n", scope->enumeration_id, drhd->address); " 0x%Lx IOMMU %d\n", scope->enumeration_id, drhd->address, iommu->seq_id); ir_parse_one_ioapic_scope(scope, iommu); } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { Loading Loading
drivers/pci/dmar.c +2 −1 Original line number Diff line number Diff line Loading @@ -806,7 +806,8 @@ int alloc_iommu(struct dmar_drhd_unit *drhd) } ver = readl(iommu->reg + DMAR_VER_REG); pr_info("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n", pr_info("IOMMU %d: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", iommu->seq_id, (unsigned long long)drhd->reg_base_addr, DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), (unsigned long long)iommu->cap, Loading
drivers/pci/intel-iommu.c +6 −3 Original line number Diff line number Diff line Loading @@ -1150,7 +1150,8 @@ static int iommu_init_domains(struct intel_iommu *iommu) unsigned long nlongs; ndomains = cap_ndoms(iommu->cap); pr_debug("Number of Domains supportd <%ld>\n", ndomains); pr_debug("IOMMU %d: Number of Domains supportd <%ld>\n", iommu->seq_id, ndomains); nlongs = BITS_TO_LONGS(ndomains); spin_lock_init(&iommu->lock); Loading Loading @@ -2319,14 +2320,16 @@ int __init init_dmars(void) */ iommu->flush.flush_context = __iommu_flush_context; iommu->flush.flush_iotlb = __iommu_flush_iotlb; printk(KERN_INFO "IOMMU 0x%Lx: using Register based " printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based " "invalidation\n", iommu->seq_id, (unsigned long long)drhd->reg_base_addr); } else { iommu->flush.flush_context = qi_flush_context; iommu->flush.flush_iotlb = qi_flush_iotlb; printk(KERN_INFO "IOMMU 0x%Lx: using Queued " printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued " "invalidation\n", iommu->seq_id, (unsigned long long)drhd->reg_base_addr); } } Loading
drivers/pci/intr_remapping.c +3 −3 Original line number Diff line number Diff line Loading @@ -832,8 +832,8 @@ static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, } printk(KERN_INFO "IOAPIC id %d under DRHD base " " 0x%Lx\n", scope->enumeration_id, drhd->address); " 0x%Lx IOMMU %d\n", scope->enumeration_id, drhd->address, iommu->seq_id); ir_parse_one_ioapic_scope(scope, iommu); } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { Loading