Commit 67f1a7a3 authored by Jordan Crouse's avatar Jordan Crouse Committed by Will Deacon
Browse files

iommu/arm-smmu: Add support for split pagetables 



Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
by the io-pgtable configuration.

Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent dd147a89

drivers/iommu/arm/arm-smmu/arm-smmu.c

+15 −4
Original line number Diff line number Diff line
@@ -552,11 +552,15 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, 
			cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr;

			cb->ttbr[1] = 0;

		} else {

			cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;

			cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID,

			cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,

						 cfg->asid);

			cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,

						 cfg->asid);



			if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)

				cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;

			else

				cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;

		}

	} else {

		cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
@@ -822,7 +826,14 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, 


	/* Update the domain's page sizes to reflect the page table format */

	domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;



	if (pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {

		domain->geometry.aperture_start = ~0UL << ias;

		domain->geometry.aperture_end = ~0UL;

	} else {

		domain->geometry.aperture_end = (1UL << ias) - 1;

	}



	domain->geometry.force_aperture = true;



	/* Initialise the context bank with our page table cfg */

drivers/iommu/arm/arm-smmu/arm-smmu.h

+19 −6
Original line number Diff line number Diff line
@@ -169,10 +169,12 @@ enum arm_smmu_cbar_type { 
#define ARM_SMMU_CB_TCR			0x30

#define ARM_SMMU_TCR_EAE		BIT(31)

#define ARM_SMMU_TCR_EPD1		BIT(23)

#define ARM_SMMU_TCR_A1			BIT(22)

#define ARM_SMMU_TCR_TG0		GENMASK(15, 14)

#define ARM_SMMU_TCR_SH0		GENMASK(13, 12)

#define ARM_SMMU_TCR_ORGN0		GENMASK(11, 10)

#define ARM_SMMU_TCR_IRGN0		GENMASK(9, 8)

#define ARM_SMMU_TCR_EPD0		BIT(7)

#define ARM_SMMU_TCR_T0SZ		GENMASK(5, 0)



#define ARM_SMMU_VTCR_RES1		BIT(31)
@@ -350,12 +352,23 @@ struct arm_smmu_domain { 


static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg)

{

	return ARM_SMMU_TCR_EPD1 |

	       FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |

	u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |

		FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |

		FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |

		FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |

		FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);



       /*

	* When TTBR1 is selected shift the TCR fields by 16 bits and disable

	* translation in TTBR0

	*/

	if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {

		tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1;

		tcr |= ARM_SMMU_TCR_EPD0;

	} else

		tcr |= ARM_SMMU_TCR_EPD1;



	return tcr;

}



static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg)